FailedChanges

Summary

  1. [msan] Fix gethostent tests (details)
  2. [msan] Remove redundant test (details)
  3. Revert rGe55410f8b260 : "AArch64/GlobalISel: Add testcase for bug 47619" (details)
  4. [SplitKit] In addDeadDef tolerate parent range that defines more lanes (details)
  5. [AMDGPU] Fix declaration parameter names to match definition (details)
  6. [AArch64] PAC/BTI code generation for LLVM generated functions (details)
  7. [Analyzer] Fix for `ExprEngine::computeObjectUnderConstruction()` for base and delegating consturctor initializers (details)
  8. [CMake][CTE] Add "check-clang-extra-..." targets to test only a particular Clang extra tool (details)
  9. [PowerPC][LLD] Extend R2 save stub to support offsets of more than 26 bits (details)
  10. [InstCombine] Add bswap tests from funnel shift intrinsics (details)
  11. [PPC] [AIX] Implement calling convention IR for C99 complex types on AIX (details)
  12. [mlir] [VectorOps] generalize printing support for integers (details)
Commit 3a98f4dca7ada4c50ebca646f2cdd7385cd778af by Vitaly Buka
[msan] Fix gethostent tests

gethostent should follow sethostent.
The file was modifiedcompiler-rt/lib/msan/tests/msan_test.cpp
Commit 7af12015ad44bccb23bd61820c8f34212467e71c by Vitaly Buka
[msan] Remove redundant test

The test needs to control intercept_strcmp option.
It's already implemented as lit.test strcmp.c.
The file was modifiedcompiler-rt/lib/msan/tests/msan_test.cpp
Commit 42bfa7c63b85e76fe16521d1671afcafaf8f64ed by llvm-dev
Revert rGe55410f8b260 : "AArch64/GlobalISel: Add testcase for bug 47619"

This reverts commit e55410f8b260a2868d600ca99fe5ee80f9cd4fc5.

This is failing on EXPENSIVE_CHECKS buildbots
The file was removedllvm/test/CodeGen/AArch64/GlobalISel/irtranslator-stack-evt-bug47619.ll
Commit b34ddfcc76e39cdad62887f648aec46c8434c648 by jay.foad
[SplitKit] In addDeadDef tolerate parent range that defines more lanes

Following on from D87757 "[SplitKit] Only copy live lanes", in
SplitEditor::addDeadDef, when we're checking whether the parent live
interval has a subrange defining the same lanes, tolerate the case
where the parent subrange defines a superset of the lanes. This can
happen when the child subrange comes from SplitEditor::buildCopy
decomposing a partial copy into a sequence of subreg copies that cover
the required lanes.

Differential Revision: https://reviews.llvm.org/D88020
The file was modifiedllvm/lib/CodeGen/SplitKit.h
The file was addedllvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask.ll
The file was modifiedllvm/lib/CodeGen/SplitKit.cpp
Commit f11f382523e096859571b61520af81b9bb1defbf by jay.foad
[AMDGPU] Fix declaration parameter names to match definition

This fixes the declaration of AMDGPULegalizerInfo::legalizeBufferLoad to
match the definition. It is still confusing that that parameter order is
different from legalizeBufferStore.

https://bugs.llvm.org/show_bug.cgi?id=47535
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
Commit a88c722e687e6780dcd6a58718350dc76fcc4cc9 by momchil.velikov
[AArch64] PAC/BTI code generation for LLVM generated functions

PAC/BTI-related codegen in the AArch64 backend is controlled by a set
of LLVM IR function attributes, added to the function by Clang, based
on command-line options and GCC-style function attributes. However,
functions, generated in the LLVM middle end (for example,
asan.module.ctor or __llvm_gcov_write_out) do not get any attributes
and the backend incorrectly does not do any PAC/BTI code generation.

This patch record the default state of PAC/BTI codegen in a set of
LLVM IR module-level attributes, based on command-line options:

* "sign-return-address", with non-zero value means generate code to
  sign return addresses (PAC-RET), zero value means disable PAC-RET.

* "sign-return-address-all", with non-zero value means enable PAC-RET
  for all functions, zero value means enable PAC-RET only for
  functions, which spill LR.

* "sign-return-address-with-bkey", with non-zero value means use B-key
  for signing, zero value mean use A-key.

This set of attributes are always added for AArch64 targets (as
opposed, for example, to interpreting a missing attribute as having a
value 0) in order to be able to check for conflicts when combining
module attributed during LTO.

Module-level attributes are overridden by function level attributes.
All the decision making about whether to not to generate PAC and/or
BTI code is factored out into AArch64FunctionInfo, there shouldn't be
any places left, other than AArch64FunctionInfo, which directly
examine PAC/BTI attributes, except AArch64AsmPrinter.cpp, which
is/will-be handled by a separate patch.

Differential Revision: https://reviews.llvm.org/D85649
The file was modifiedllvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-1.ll
The file was modifiedllvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-3.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64BranchTargets.cpp
The file was modifiedllvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-8.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64FrameLowering.cpp
The file was addedllvm/test/CodeGen/AArch64/pacbti-llvm-generated-funcs-1.ll
The file was modifiedclang/lib/CodeGen/CodeGenModule.cpp
The file was modifiedllvm/test/CodeGen/AArch64/machine-outliner-2fixup-blr-terminator.mir
The file was modifiedllvm/lib/Target/AArch64/AArch64MachineFunctionInfo.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.cpp
The file was modifiedllvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-4.ll
The file was modifiedllvm/test/CodeGen/AArch64/bti-branch-relaxation.ll
The file was modifiedllvm/test/CodeGen/AArch64/branch-target-enforcement-indirect-calls.ll
The file was modifiedllvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-5.ll
The file was modifiedclang/lib/CodeGen/CGDeclCXX.cpp
The file was modifiedllvm/test/CodeGen/AArch64/branch-target-enforcement.mir
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
The file was removedclang/test/CodeGenCXX/aarch64-sign-return-address-static-ctor.cpp
The file was addedllvm/test/CodeGen/AArch64/pacbti-module-attrs.ll
The file was modifiedclang/test/CodeGen/aarch64-branch-protection-attr.c
The file was modifiedllvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h
The file was modifiedllvm/test/CodeGen/AArch64/machine-outliner-bti.mir
The file was modifiedllvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-7.ll
The file was modifiedclang/test/CodeGen/aarch64-sign-return-address.c
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.td
The file was modifiedclang/lib/CodeGen/TargetInfo.cpp
The file was modifiedllvm/test/CodeGen/AArch64/patchable-function-entry-bti.ll
The file was modifiedllvm/test/CodeGen/AArch64/machine-outliner-outline-bti.ll
The file was addedllvm/test/CodeGen/AArch64/pacbti-llvm-generated-funcs-2.ll
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
The file was modifiedllvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-0.ll
Commit facad21b29839a08fdf448eb4dd5a4e31e293b9b by adam.balogh
[Analyzer] Fix for `ExprEngine::computeObjectUnderConstruction()` for base and delegating consturctor initializers

For /C++/ constructor initializers `ExprEngine:computeUnderConstruction()`
asserts that they are all member initializers. This is not neccessarily
true when this function is used to get the return value for the
construction context thus attempts to fetch return values of base and
delegating constructor initializers result in assertions. This small
patch fixes this issue.

Differential Revision: https://reviews.llvm.org/D85351
The file was modifiedclang/lib/StaticAnalyzer/Core/ExprEngineCXX.cpp
The file was modifiedclang/unittests/StaticAnalyzer/TestReturnValueUnderConstruction.cpp
Commit 9d2ef5e74eea2247657431f44152f1f83ed99b84 by whisperity
[CMake][CTE] Add "check-clang-extra-..." targets to test only a particular Clang extra tool

Create targets `check-clang-extra-clang-tidy`, `check-clang-extra-clang-query`
similar to how `check-clang-sema`, `check-clang-parser`, etc. are
auto-generated from the directory structure.

This allows running only a particular sub-tool's tests, not having to wait
through the entire `check-clang-tools` execution.

Differential Revision: http://reviews.llvm.org/D84176
The file was modifiedclang-tools-extra/test/CMakeLists.txt
Commit d224175230d1ab232cfdf71f9da63a732f405c91 by stefanp
[PowerPC][LLD] Extend R2 save stub to support offsets of more than 26 bits

The R2 save stub will now support offsets up to 64 bits.

There are three cases that will be used.
1) The offset fits in 26 bits.
```
b <26 bit offset>
```
2) The offset does not fit in 26 bits but fits in 34 bits.
```
paddi r12, 0, <34 bit offset>, 1
mtctr r12
bctr
```
3) The offset does not fit in 34 bits. Since this is an R2 save stub we can use
the TOC in R2. We are not loading the offset but the actual address we want to
branch to.
```
addis r12, r2, <address in TOC lo>
ld r12 <address in TOC hi>(r12)
mtctr r12
bctr
```

In case 1) the stub is only 8 bytes while in cases 2) and 3) the stub will be
20 bytes.

Reviewed By: MaskRay, sfertile, NeHuang

Differential Revision: https://reviews.llvm.org/D87916
The file was modifiedlld/ELF/Thunks.cpp
The file was modifiedlld/test/ELF/ppc64-toc-call-to-pcrel-long-jump.s
Commit 852447650c75de5f3e9c53a2659589cd2fd36b4d by llvm-dev
[InstCombine] Add bswap tests from funnel shift intrinsics

Based on (WIP) patch in D87452 - I'm intending to add the intrinsics handling to collectBitParts as a separate patch to make the changes clearer.
The file was modifiedllvm/test/Transforms/InstCombine/bswap.ll
Commit f330d9f163f644b968c6aa5884dc1be5efda20a1 by zarko
[PPC] [AIX] Implement calling convention IR for C99 complex types on AIX

Add AIX calling convention logic to Clang for C99 complex types on AIX

Differential Revision: https://reviews.llvm.org/D88130
The file was modifiedclang/lib/CodeGen/TargetInfo.cpp
The file was removedclang/test/CodeGen/aix-complex.c
The file was modifiedclang/test/CodeGen/powerpc-c99complex.c
Commit b8880f5f97bf1628b2c9606e96abcd612dc7d747 by ajcbik
[mlir] [VectorOps] generalize printing support for integers

This generalizes printing beyond just i1,i32,i64 and also accounts
for signed and unsigned interpretation in the output.

Reviewed By: nicolasvasilache

Differential Revision: https://reviews.llvm.org/D88290
The file was modifiedmlir/lib/ExecutionEngine/CRunnerUtils.cpp
The file was addedmlir/integration_test/Dialect/Vector/CPU/test-print-int.mlir
The file was modifiedmlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
The file was modifiedmlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir