1. [SystemZ]  Support bare nop instructions (details)
  2. [MLIR][SPIRV] Support different function control in (de)serialization (details)
  3. [X86] Support Intel Key Locker (details)
  4. [gn build] Port 413577a8790 (details)
  5. [InstCombine] recognizeBSwapOrBitReverseIdiom - assert for correct bit providence indices. NFCI. (details)
  6. [InstCombine] recognizeBSwapOrBitReverseIdiom - recognise zext(bswap(trunc(x))) patterns (PR39793) (details)
  7. [mlir] Added support for rank reducing subviews (details)
  8. [NFC][ARM] Add more LowOverheadLoop tests. (details)
  9. [mlir][Linalg] Tile sizes for Conv ops vectorization added as pass arguments (details)
  10. [SCEV] Verify that all mapped SCEV AddRecs refer to valid loops. (details)
Commit 9f5da55f5d9299a76a4dfb67ef0324dbc1900826 by paulsson
[SystemZ]  Support bare nop instructions

Add support of "nop" and "nopr" (without operands) to assembler.

Review: Ulrich Weigand
The file was modifiedllvm/lib/Target/SystemZ/
The file was modifiedllvm/test/MC/SystemZ/insn-good.s
Commit 8c05c7c8d87c7ab02fca2a789dfcca4976c6601b by georgemitenk0v
[MLIR][SPIRV] Support different function control in (de)serialization

Added support for different function control
in serialization and deserialization.

Reviewed By: mravishankar

Differential Revision:
The file was modifiedmlir/lib/Dialect/SPIRV/Serialization/Serializer.cpp
The file was modifiedmlir/lib/Dialect/SPIRV/Serialization/Deserializer.cpp
The file was modifiedmlir/test/Dialect/SPIRV/Serialization/module.mlir
Commit 413577a8790407d75ba834fa5668c2632fe1851e by xiang1.zhang
[X86] Support Intel Key Locker

Key Locker provides a mechanism to encrypt and decrypt data with an AES key without having access
to the raw key value by converting AES keys into “handles”. These handles can be used to perform the
same encryption and decryption operations as the original AES keys, but they only work on the current
system and only until they are revoked. If software revokes Key Locker handles (e.g., on a reboot),
then any previous handles can no longer be used.

Reviewed By: craig.topper

Differential Revision:
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was addedllvm/test/MC/Disassembler/X86/KEYLOCKER/Keylocker-x86-64-intel.txt
The file was modifiedllvm/lib/Support/Host.cpp
The file was modifiedllvm/utils/TableGen/IntrinsicEmitter.cpp
The file was addedllvm/test/MC/X86/KEYLOCKER/keylocker-att.s
The file was addedllvm/lib/Target/X86/
The file was modifiedclang/lib/Basic/Targets/X86.cpp
The file was modifiedclang/lib/Basic/Targets/X86.h
The file was addedclang/lib/Headers/keylocker_wide_intrin.h
The file was modifiedclang/test/CodeGen/attr-target-x86.c
The file was modifiedllvm/lib/Support/X86TargetParser.cpp
The file was addedllvm/test/MC/Disassembler/X86/KEYLOCKER/Keylocker-x86-64-att.txt
The file was addedllvm/test/MC/X86/KEYLOCKER/x86-64-keylocker-intel.s
The file was modifiedclang/lib/Headers/immintrin.h
The file was modifiedllvm/lib/Target/X86/
The file was modifiedllvm/lib/Target/X86/
The file was modifiedclang/include/clang/Basic/BuiltinsX86.def
The file was addedclang/lib/Headers/keylockerintrin.h
The file was modifiedllvm/include/llvm/Support/X86TargetParser.def
The file was addedllvm/test/CodeGen/X86/keylocker-intrinsics.ll
The file was addedllvm/test/MC/X86/KEYLOCKER/x86-64-keylocker-att.s
The file was modifiedclang/lib/CodeGen/CGBuiltin.cpp
The file was modifiedclang/test/Driver/x86-target-features.c
The file was modifiedclang/test/Preprocessor/x86_target_features.c
The file was modifiedllvm/include/llvm/IR/
The file was modifiedclang/include/clang/Driver/
The file was addedllvm/lib/Target/X86/
The file was addedllvm/test/MC/X86/KEYLOCKER/keylocker-intel.s
The file was modifiedllvm/lib/IR/Function.cpp
The file was addedllvm/test/MC/Disassembler/X86/KEYLOCKER/Keylocker-x86-32-intel.txt
The file was addedllvm/test/MC/Disassembler/X86/KEYLOCKER/Keylocker-x86-32-att.txt
The file was modifiedclang/lib/Headers/CMakeLists.txt
The file was addedclang/test/CodeGen/X86/keylocker.c
The file was modifiedllvm/lib/Target/X86/X86Subtarget.h
Commit e39d7884a1f5c5c7136ba2e493e9ac313ccc78ed by llvmgnsyncbot
[gn build] Port 413577a8790
The file was modifiedllvm/utils/gn/secondary/clang/lib/Headers/
Commit ec3f24d4538d1c262377331c7b35ea66e023cf98 by llvm-dev
[InstCombine] recognizeBSwapOrBitReverseIdiom - assert for correct bit providence indices. NFCI.

As suggested by @spatel on D88316
The file was modifiedllvm/lib/Transforms/Utils/Local.cpp
Commit af47d40b9c68744eb66aa2ef779065e946aaa099 by llvm-dev
[InstCombine] recognizeBSwapOrBitReverseIdiom - recognise zext(bswap(trunc(x))) patterns (PR39793)

PR39793 demonstrated an issue where we fail to recognize 'partial' bswap patterns of the lower bytes of an integer source.

In fact, most of this is already in place collectBitParts suitably tags zero bits, so we just need to correctly handle this case by finding the zero'd upper bits and reducing the bswap pattern just to the active demanded bits.

Differential Revision:
The file was modifiedllvm/test/Transforms/InstCombine/bswap.ll
The file was modifiedllvm/lib/Transforms/Utils/Local.cpp
Commit 14088a6f5d1ae597960833a366beb9acee8d65cb by limo
[mlir] Added support for rank reducing subviews

This commit adds support for subviews which enable to reduce resulting rank
by dropping static dimensions of size 1.

Differential Revision:
The file was modifiedmlir/lib/Dialect/StandardOps/IR/Ops.cpp
The file was modifiedmlir/test/IR/invalid-ops.mlir
The file was modifiedmlir/lib/Dialect/Vector/VectorTransforms.cpp
The file was modifiedmlir/include/mlir/Dialect/StandardOps/IR/
The file was modifiedmlir/test/IR/core-ops.mlir
Commit 3cbd01ddb9372b725dcea3dd5fed21ef5b3d9578 by sam.parker
[NFC][ARM] Add more LowOverheadLoop tests.
The file was addedllvm/test/CodeGen/Thumb2/LowOverheadLoops/biquad-cascade-default.mir
The file was addedllvm/test/CodeGen/Thumb2/LowOverheadLoops/biquad-cascade-optsize.mir
The file was addedllvm/test/CodeGen/Thumb2/LowOverheadLoops/biquad-cascade-optsize-strd-lr.mir
Commit 0b17d4754a94b7129c2483762acd586783802b12 by limo
[mlir][Linalg] Tile sizes for Conv ops vectorization added as pass arguments

Current setup for conv op vectorization does not enable user to specify tile
sizes as well as dimensions for vectorization. In this commit we change that by
adding tile sizes as pass arguments. Every dimension with corresponding tile
size > 1 is automatically vectorized.

Differential Revision:
The file was modifiedmlir/integration_test/Dialect/Linalg/CPU/test-conv-2d-nhwc-call.mlir
The file was modifiedmlir/integration_test/Dialect/Linalg/CPU/test-conv-3d-call.mlir
The file was modifiedmlir/integration_test/Dialect/Linalg/CPU/test-conv-1d-nwc-call.mlir
The file was modifiedmlir/test/Conversion/LinalgToVector/linalg-to-vector.mlir
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp
The file was modifiedmlir/test/lib/Transforms/TestConvVectorization.cpp
The file was modifiedmlir/integration_test/Dialect/Linalg/CPU/test-conv-1d-call.mlir
The file was modifiedmlir/integration_test/Dialect/Linalg/CPU/test-conv-3d-ndhwc-call.mlir
The file was modifiedmlir/integration_test/Dialect/Linalg/CPU/test-conv-2d-nchw-call.mlir
The file was modifiedmlir/integration_test/Dialect/Linalg/CPU/test-conv-2d-call.mlir
The file was modifiedmlir/integration_test/Dialect/Linalg/CPU/test-conv-1d-ncw-call.mlir
The file was modifiedmlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h
The file was modifiedmlir/integration_test/Dialect/Linalg/CPU/test-conv-3d-ncdhw-call.mlir
Commit 0eab9d5823815c6520697f8d725c402c88e5d050 by flo
[SCEV] Verify that all mapped SCEV AddRecs refer to valid loops.

This check helps to guard against cases where expressions referring to
invalidated/deleted loops are not properly invalidated.

The additional check is motivated by the reproducer shared for 8fdac7cb7abb
and I think in general make sense as a sanity check.

Reviewed By: reames

Differential Revision:
The file was modifiedllvm/lib/Analysis/ScalarEvolution.cpp