FailedChanges

Summary

  1. InstCombine] collectBitParts - cleanup variable names. NFCI. (details)
  2. [InstCombine] recognizeBSwapOrBitReverseIdiom - use ArrayRef::back() helper. NFCI. (details)
  3. [RDA] isSafeToDefRegAt: Look at global uses (details)
  4. [InstCombine] recognizeBSwapOrBitReverseIdiom - cleanup bswap/bitreverse detection loop. NFCI. (details)
  5. [InstCombine] Add PR47191 bswap tests (details)
  6. [lldb] Fix FreeBSD Arm Process Plugin build (details)
  7. [VPlan] Change recipes to inherit from VPUser instead of a member var. (details)
  8. [lldb] [Process/NetBSD] Fix operating on ftag register (details)
  9. [InstCombine] recognizeBSwapOrBitReverseIdiom - remove unnecessary cast. NFCI. (details)
  10. [InstCombine] Remove %tmp variable names from bswap tests (details)
  11. [InstCombine] recognizeBSwapOrBitReverseIdiom - merge the regular/trunc+zext paths. NFCI. (details)
  12. [clangd] Fix invalid UTF8 when extracting doc comments. (details)
  13. [PowerPC] Remove support for VRSAVE save/restore/update. (details)
  14. [GlobalISel] Fix incorrect setting of ValNo when splitting (details)
  15. Move AffineMapAttr into BaseOps.td (details)
  16. [sanitizers] Fix internal__exit on Solaris (details)
  17. [NFC][FE] Replace TypeSize with StorageUnitSize (details)
  18. Reapply "RegAllocFast: Rewrite and improve" (details)
  19. RegAllocFast: Add extra DBG_VALUE for live out spills (details)
  20. LiveDebugValues: Fix typos and indentation (details)
  21. GlobalISel: Assert if MoreElements uses a non-vector type (details)
  22. [InstCombine] Remove %tmp variable names from bswap-fold tests (details)
Commit 05290eead3f95e02700890321ccf6719770f91fe by llvm-dev
InstCombine] collectBitParts - cleanup variable names. NFCI.

Fix a number of WShadow warnings (I was used as the instruction and index......) and fix cases to match style.

Also, replaced the Bit APInt mask check in AND instructions with a direct APInt[] bit check.
The file was modifiedllvm/lib/Transforms/Utils/Local.cpp
Commit 413b4998bd722ab671e29e6dff5d458d1869f39b by llvm-dev
[InstCombine] recognizeBSwapOrBitReverseIdiom - use ArrayRef::back() helper. NFCI.

Post-commit feedback on D88316
The file was modifiedllvm/lib/Transforms/Utils/Local.cpp
Commit 3f88c10a6b25668bb99f5eee7867dcbf37df973c by sam.parker
[RDA] isSafeToDefRegAt: Look at global uses

We weren't looking at global uses of a value, so we could happily
overwrite the register incorrectly.

Differential Revision: https://reviews.llvm.org/D88554
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/biquad-cascade-optsize-strd-lr.mir
The file was modifiedllvm/lib/CodeGen/ReachingDefAnalysis.cpp
Commit 621c6c89627972d52796e64a9476a7d05f22f2cd by llvm-dev
[InstCombine] recognizeBSwapOrBitReverseIdiom - cleanup bswap/bitreverse detection loop. NFCI.

Early out if both pattern matches have failed (or we don't want them). Fix case of bit index iterator (and avoid Wshadow issue).
The file was modifiedllvm/lib/Transforms/Utils/Local.cpp
Commit 08c5720405d5204ec2329b7f6c561062c7dddee2 by llvm-dev
[InstCombine] Add PR47191 bswap tests
The file was modifiedllvm/test/Transforms/InstCombine/bswap.ll
Commit f794160c6cb7da4b5ef354a91fe498341f651d36 by emaste
[lldb] Fix FreeBSD Arm Process Plugin build

Add a missing include and some definitions in 769533216666.

Patch by: Brooks Davis

Reviewed by: labath

Differential Revision: https://reviews.llvm.org/D88453
The file was modifiedlldb/source/Plugins/Process/FreeBSD/RegisterContextPOSIXProcessMonitor_arm.h
The file was modifiedlldb/source/Plugins/Process/FreeBSD/RegisterContextPOSIXProcessMonitor_arm.cpp
Commit d8563654701c79fb9ab28ecf94567d9934baed05 by flo
[VPlan] Change recipes to inherit from VPUser instead of a member var.

Now that VPUser is not inheriting from VPValue, we can take the next
step and turn the recipes that already manage their operands via VPUser
into VPUsers directly. This is another small step towards traversing
def-use chains in VPlan.

This is NFC with respect to the generated code, but makes the interface
more powerful.
The file was modifiedllvm/unittests/Transforms/Vectorize/VPlanTest.cpp
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
The file was modifiedllvm/lib/Transforms/Vectorize/VPlan.h
The file was modifiedllvm/lib/Transforms/Vectorize/VPlanValue.h
Commit 762e8f9bbdaf43300dbc75637a8bce1ce643cc06 by mgorny
[lldb] [Process/NetBSD] Fix operating on ftag register
The file was modifiedlldb/source/Plugins/Process/NetBSD/NativeRegisterContextNetBSD_x86_64.cpp
Commit d5545a8993489ee426b757482a64c9373cf7cf38 by llvm-dev
[InstCombine] recognizeBSwapOrBitReverseIdiom - remove unnecessary cast. NFCI.
The file was modifiedllvm/lib/Transforms/Utils/Local.cpp
Commit 7fcad5583a12026ce19afe487681753ac633064a by llvm-dev
[InstCombine] Remove %tmp variable names from bswap tests

Appease update_test_checks script that was complaining about potential %TMP clashes
The file was modifiedllvm/test/Transforms/InstCombine/bswap.ll
Commit c722b3259690d3aad20f31d0ffe6c12b1416bccc by llvm-dev
[InstCombine] recognizeBSwapOrBitReverseIdiom - merge the regular/trunc+zext paths. NFCI.

There doesn't seem to be any good reason for having a separate path for when we bswap/bitreverse at a smaller size than the destination size - so merge these to make the instruction generation a lot clearer.
The file was modifiedllvm/lib/Transforms/Utils/Local.cpp
Commit 216af81c39d1cc4e90af7b991d517c4c7acc912e by sam.mccall
[clangd] Fix invalid UTF8 when extracting doc comments.

Differential Revision: https://reviews.llvm.org/D88567
The file was modifiedclang-tools-extra/clangd/unittests/CodeCompletionStringsTests.cpp
The file was modifiedclang-tools-extra/clangd/CodeCompletionStrings.cpp
The file was modifiedclang-tools-extra/clangd/unittests/SymbolCollectorTests.cpp
Commit dfb717da1f794c235b81a985a57dc238c82318e6 by sd.fertile
[PowerPC] Remove support for VRSAVE save/restore/update.

After removal of Darwin as a PowerPC subtarget, the VRSAVE
save/restore/spill/update code is no longer needed by any supported
subtarget, so remove it while keeping support for vrsave and related instruction
aliases for inline asm. I've pre-commited tests to document the existing vrsave
handling in relation to @llvm.eh.unwind.init and inline asm usage, as
well as a test which shows a beahviour change on AIX related to
returning vector type as we were wrongly emiting VRSAVE_UPDATE on AIX.
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrInfo.td
The file was modifiedllvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h
The file was modifiedllvm/lib/Target/PowerPC/PPCRegisterInfo.h
The file was modifiedllvm/lib/Target/PowerPC/PPCISelLowering.cpp
The file was modifiedllvm/lib/Target/PowerPC/README_ALTIVEC.txt
The file was modifiedllvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrInfo.cpp
The file was modifiedllvm/test/CodeGen/PowerPC/aix-vector-return.ll
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrInfo.h
The file was modifiedllvm/lib/Target/PowerPC/PPCFrameLowering.cpp
Commit 43d239d0fadb1f8ea297580ca39dfbee96c913c1 by mikael.holmen
[GlobalISel] Fix incorrect setting of ValNo when splitting

Before, for each original argument i, ValNo was set to i + PartIdx, but
ValNo is intended to reflect the index of the value before splitting.
Hence, ValNo should always be set to i and not consider the PartIdx.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D86511
The file was modifiedllvm/lib/CodeGen/GlobalISel/CallLowering.cpp
Commit f33f8a2b30325d89c4b7daef1b7d11d6da38fd56 by benny.kra
Move AffineMapAttr into BaseOps.td

AffineMapAttr is already part of base, it's just impossible to refer to
it from ODS without pulling in the definition from Affine dialect.

Differential Revision: https://reviews.llvm.org/D88555
The file was modifiedmlir/include/mlir/IR/OpBase.td
The file was modifiedmlir/include/mlir/Dialect/Affine/IR/AffineOps.td
The file was modifiedmlir/include/mlir/Dialect/Vector/VectorOps.td
The file was modifiedmlir/include/mlir/Dialect/GPU/ParallelLoopMapperAttr.td
The file was modifiedmlir/include/mlir/Dialect/Linalg/IR/LinalgStructuredOps.td
The file was removedmlir/include/mlir/Dialect/Affine/IR/AffineOpsBase.td
The file was modifiedmlir/test/lib/Dialect/Test/TestOps.td
The file was modifiedmlir/include/mlir/Dialect/Linalg/IR/LinalgOps.td
Commit dc261d23d07cccfa7b10a3d1a43903138aee94dc by ro
[sanitizers] Fix internal__exit on Solaris
`TestCases/log-path_test.cpp` currently `FAIL`s on Solaris:

  $ env ASAN_OPTIONS=log_path=`for((i=0;i<10000;i++)); do echo -n $i; done`  ./log-path_test.cpp.tmp
  ==5031==ERROR: Path is too long: 01234567...
  Segmentation Fault (core dumped)

The `SEGV` happens here:

  Thread 2 received signal SIGSEGV, Segmentation fault.
  [Switching to Thread 1 (LWP 1)]
  0x00000000 in ?? ()
  (gdb) where
  #0  0x00000000 in ?? ()
  #1  0x080a1e63 in __interceptor__exit (status=1)
      at /vol/gcc/src/llvm/llvm/local/projects/compiler-rt/lib/asan/../sanitizer_common/sanitizer_common_interceptors.inc:3808
  #2  0x08135ea8 in __sanitizer::internal__exit (exitcode=1)
      at /vol/gcc/src/llvm/llvm/local/projects/compiler-rt/lib/sanitizer_common/sanitizer_solaris.cc:139

when `__interceptor__exit` tries to call `__interception::real__exit` which
is `NULL` at this point because the interceptors haven't been initialized yet.

Ultimately, the problem lies elsewhere, however: `internal__exit` in
`sanitizer_solaris.cpp` calls `_exit` itself since there doesn't exit a
non-intercepted version in `libc`.  Using the `syscall` interface instead
isn't usually an option on Solaris because that interface isn't stable.
However, in the case of `SYS_exit` it can be used nonetheless: `SYS_exit`
has remained unchanged since at least Solaris 2.5.1 in 1996, and this is
what this patch does.

Tested on `amd64-pc-solaris2.11`.

Differential Revision: https://reviews.llvm.org/D88404
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_solaris.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_linux.cpp
Commit 944691f0b7fa8d99790a4544545e55f014c37295 by Xiangling.Liao
[NFC][FE] Replace TypeSize with StorageUnitSize

On some targets like AIX, last bitfield size is not always equal to last
bitfield type size. Some bitfield like bool will have the same alignment
as [unsigned]. So we'd like to use a more general term `StorageUnit` to
replace type in this field.

Differential Revision: https://reviews.llvm.org/D88260
The file was modifiedclang/lib/AST/RecordLayoutBuilder.cpp
Commit 89baeaef2fa9a2441d087a218ac82e11a5d4e548 by Matthew.Arsenault
Reapply "RegAllocFast: Rewrite and improve"

This reverts commit 73a6a164b84a8195defbb8f5eeb6faecfc478ad4.
The file was modifiedllvm/test/CodeGen/PowerPC/elf-common.ll
The file was modifiedllvm/test/CodeGen/X86/mixed-ptr-sizes.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/long_ambiguous_chain_s64.ll
The file was modifiedllvm/test/CodeGen/Mips/atomic.ll
The file was modifiedllvm/test/CodeGen/X86/pr44749.ll
The file was modifiedllvm/test/CodeGen/ARM/fast-isel-ldr-str-thumb-neg-index.ll
The file was modifiedllvm/test/CodeGen/X86/regalloc-fast-missing-live-out-spill.mir
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/mul.ll
The file was modifiedllvm/test/CodeGen/X86/stack-protector-msvc.ll
The file was modifiedllvm/test/CodeGen/ARM/thumb-big-stack.ll
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The file was modifiedllvm/test/CodeGen/AMDGPU/reserve-vgpr-for-sgpr-spill.ll
The file was modifiedllvm/test/DebugInfo/X86/spill-indirect-nrvo.ll
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The file was modifiedllvm/test/CodeGen/X86/fast-isel-cmp-branch.ll
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The file was modifiedllvm/test/CodeGen/PowerPC/vsx-args.ll
The file was modifiedllvm/test/CodeGen/AArch64/unwind-preserved-from-mir.mir
The file was modifiedllvm/test/CodeGen/ARM/swifterror.ll
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The file was modifiedllvm/test/CodeGen/ARM/stack-guard-reassign.ll
The file was modifiedllvm/test/CodeGen/Thumb2/high-reg-spill.mir
The file was modifiedllvm/test/CodeGen/PowerPC/spill-nor0.ll
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The file was modifiedllvm/test/CodeGen/Mips/Fast-ISel/callabi.ll
The file was modifiedllvm/test/CodeGen/ARM/pr47454.ll
The file was modifiedllvm/test/CodeGen/ARM/legalize-bitcast.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vector-spill.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/aggregate_struct_return.ll
The file was modifiedllvm/test/CodeGen/X86/pr34592.ll
The file was modifiedllvm/test/CodeGen/Hexagon/vect/vect-load-v4i16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/spill-m0.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/add_vec.ll
The file was modifiedllvm/test/DebugInfo/X86/subreg.ll
The file was modifiedllvm/test/CodeGen/SPARC/fp16-promote.ll
The file was modifiedllvm/test/DebugInfo/AArch64/frameindices.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/long_ambiguous_chain_s32.ll
The file was modifiedllvm/test/CodeGen/X86/swifterror.ll
The file was addedllvm/test/CodeGen/AMDGPU/fastregalloc-illegal-subreg-physreg.mir
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/add.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/global_address_pic.ll
The file was modifiedllvm/test/CodeGen/Mips/atomic64.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/load_4_unaligned.ll
The file was modifiedllvm/test/CodeGen/X86/2013-10-14-FastISel-incorrect-vreg.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/float_constants.ll
The file was modifiedllvm/test/CodeGen/X86/pr32345.ll
The file was modifiedllvm/test/CodeGen/X86/atomic6432.ll
The file was modifiedllvm/test/CodeGen/AArch64/fast-isel-cmpxchg.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/branch.ll
The file was modifiedllvm/test/CodeGen/X86/pr27591.ll
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/darwin-tls-call-clobber.ll
The file was modifiedllvm/test/CodeGen/PowerPC/fp-int128-fp-combine.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll
The file was modifiedllvm/test/DebugInfo/X86/sret.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/wwm-reserved.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-fast-isel-br.ll
The file was modifiedllvm/test/CodeGen/X86/pr32241.ll
The file was modifiedllvm/test/DebugInfo/Mips/prologue_end.ll
The file was modifiedlldb/test/Shell/SymbolFile/NativePDB/disassembly.cpp
The file was modifiedllvm/test/CodeGen/PowerPC/p9-vinsert-vextract.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64_32-null.ll
The file was modifiedllvm/test/CodeGen/X86/fast-isel-select.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-fast-isel-call.ll
The file was modifiedllvm/test/DebugInfo/ARM/prologue_end.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/bitwise.ll
The file was modifiedllvm/test/CodeGen/SystemZ/swifterror.ll
The file was modifiedllvm/test/CodeGen/X86/fast-isel-select-sse.ll
The file was modifiedllvm/test/CodeGen/AArch64/popcount.ll
The file was modifiedllvm/test/CodeGen/X86/volatile.ll
The file was modifiedllvm/test/DebugInfo/X86/fission-ranges.ll
The file was modifiedllvm/test/CodeGen/PowerPC/stack-guard-reassign.ll
The file was modifiedllvm/test/CodeGen/ARM/Windows/alloca.ll
The file was modifiedllvm/test/CodeGen/X86/avx512-mask-zext-bugfix.ll
The file was modifiedllvm/test/DebugInfo/AArch64/prologue_end.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/rem_and_div.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/var_arg.ll
The file was modifiedllvm/test/CodeGen/AArch64/unwind-preserved.ll
The file was modifiedllvm/test/CodeGen/Mips/Fast-ISel/memtest1.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/brindirect.ll
The file was modifiedllvm/test/CodeGen/PowerPC/fp-strict-fcmp-noopt.ll
The file was modifiedllvm/test/CodeGen/X86/atomic64.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/fastregalloc-self-loop-heuristic.mir
The file was modifiedllvm/test/CodeGen/ARM/fast-isel-select.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sub_vec.ll
The file was modifiedllvm/test/CodeGen/X86/atomic32.ll
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The file was modifiedllvm/test/CodeGen/ARM/crash-greedy-v6.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/store_4_unaligned.ll
The file was modifiedllvm/test/DebugInfo/X86/op_deref.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/spill192.mir
The file was modifiedllvm/test/CodeGen/X86/pr39733.ll
The file was modifiedllvm/test/CodeGen/ARM/2010-08-04-StackVariable.ll
The file was modifiedllvm/test/CodeGen/X86/2010-06-28-FastAllocTiedOperand.ll
The file was addedllvm/test/CodeGen/X86/bug47278-eflags-error.mir
The file was modifiedllvm/lib/CodeGen/RegAllocFast.cpp
The file was modifiedllvm/test/CodeGen/AArch64/arm64_32-fastisel.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/indirect-addressing-term.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/store_split_because_of_memsize_or_align.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/test_TypeInfoforMF.ll
Commit a66fca44ac926b25820f0e9344db1947d966291b by Matthew.Arsenault
RegAllocFast: Add extra DBG_VALUE for live out spills

This allows LiveDebugValues to insert the proper DBG_VALUEs in live
out blocks if a spill is inserted before the use of a
register. Previously, this would see the register use as the last
DBG_VALUE, even though the stack slot should be treated as the live
out value.

This avoids an lldb test regression when D52010 is re-applied.
The file was modifiedllvm/test/DebugInfo/X86/parameters.ll
The file was modifiedllvm/test/DebugInfo/X86/subreg.ll
The file was modifiedllvm/test/DebugInfo/X86/sret.ll
The file was modifiedllvm/test/DebugInfo/X86/fission-ranges.ll
The file was modifiedllvm/lib/CodeGen/RegAllocFast.cpp
The file was addedllvm/test/CodeGen/X86/fast-regalloc-live-out-debug-values.mir
The file was modifiedllvm/test/DebugInfo/X86/op_deref.ll
Commit d93459992e559e774e7b14208e5bd8bf27a58280 by Matthew.Arsenault
LiveDebugValues: Fix typos and indentation
The file was modifiedllvm/lib/CodeGen/LiveDebugValues/VarLocBasedImpl.cpp
Commit 5aa1119537fe6569b54d0da4d9d649a6940decff by Matthew.Arsenault
GlobalISel: Assert if MoreElements uses a non-vector type
The file was modifiedllvm/lib/CodeGen/GlobalISel/LegalizerInfo.cpp
Commit 2ef73025afda6481625b74eb99cdbc2eb1cfef95 by llvm-dev
[InstCombine] Remove %tmp variable names from bswap-fold tests

Appease update_test_checks script that was complaining about potential %TMP clashes
The file was modifiedllvm/test/Transforms/InstCombine/bswap-fold.ll