SuccessChanges

Changes from Git (git http://labmaster3.local/git/llvm-project.git)

Summary

  1. [LV][NFC] Some refactoring and renaming to facilitate next change. (details)
  2. [LV][NFC] Keep dominator tree up to date during vectorization. (details)
  3. [ARM] MVE sink ICmp test. NFC (details)
  4. [ARM] Sink splat to ICmp (details)
  5. Revert "[MIPS GlobalISel] Select bitreverse" (details)
  6. [PowerPC] Legalize rounding nodes (details)
Commit 1b6286b945a5e941f4208f6f242e31ef6f7e55bc by evgueni.brevnov
[LV][NFC] Some refactoring and renaming to facilitate next change.
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Commit 948e745270de615cb83bc9c68cdfa4da62925d0f by evgueni.brevnov
[LV][NFC] Keep dominator tree up to date during vectorization.
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
The file was modifiedllvm/lib/Transforms/Vectorize/VPlan.cpp
The file was modifiedllvm/lib/Transforms/Vectorize/VPlan.h
Commit a5a141544d0b3ce64c97ef9bb88ae5231e427b9f by david.green
[ARM] MVE sink ICmp test. NFC
The file was addedllvm/test/CodeGen/Thumb2/mve-pred-threshold.ll
Commit b4abe7afbf5272d56ec8adb39fdccf1e2df48a88 by david.green
[ARM] Sink splat to ICmp
This adds ICmp to the list of instructions that we sink a splat to in a
loop, allowing the register forms of instructions to be selected more
often. It does not add FCmp yet as the results look a little odd, trying
to keep the register in an float reg and having to move it back to a
GPR.
Differential Revision: https://reviews.llvm.org/D70997
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/fast-fp-loops.ll
The file was modifiedllvm/lib/Target/ARM/MVETailPredication.cpp
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
The file was modifiedllvm/test/CodeGen/Thumb2/mve-pred-threshold.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/cond-vector-reduce-mve-codegen.ll
Commit 32cc14100e802fddd9f88e7a862250ce3108a583 by gribozavr
Revert "[MIPS GlobalISel] Select bitreverse"
This reverts commit dbc136e0fe7e14c64dcb78e72321bb41af60afa4. It broke
buildbots:
http://lab.llvm.org:8011/builders/clang-x86_64-debian-fast/builds/21066
The file was removedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/bitreverse.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitreverse.mir
The file was modifiedllvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
The file was modifiedllvm/lib/Target/Mips/MipsLegalizerInfo.cpp
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
The file was removedllvm/test/CodeGen/Mips/GlobalISel/legalizer/bitreverse.mir
Commit 0f0330a7870929558b2a2571ab28d242e719142e by nemanja.i.ibm
[PowerPC] Legalize rounding nodes
VSX provides a full complement of rounding instructions yet we somehow
ended up with some of them legal and others not. This just legalizes all
of the FP rounding nodes and the FP -> int rounding nodes with unsafe
math.
Differential revision: https://reviews.llvm.org/D69949
The file was addedllvm/test/CodeGen/PowerPC/scalar-rounding-ops.ll
The file was modifiedllvm/lib/Target/PowerPC/PPCISelLowering.cpp
The file was modifiedllvm/test/CodeGen/PowerPC/fp-int128-fp-combine.ll
The file was modifiedllvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrVSX.td
The file was modifiedllvm/test/CodeGen/PowerPC/rounding-ops.ll