SuccessChanges

Changes from Git (git http://labmaster3.local/git/llvm-project.git)

Summary

  1. [MC] Delete MCFragment::isDummy. NFC (details)
  2. [DAGCombine] Don't check the legality of type when combine the (details)
  3. [MC] Reorder MCFragment members to decrease padding (details)
Commit 2c053109fa83dc260042552c9132f3f528eb894e by maskray
[MC] Delete MCFragment::isDummy. NFC
isa<...>, dyn_cast<...> and cast<...> are used by other fragments. Don't
make MCDummyFragment special.
The file was modifiedllvm/include/llvm/MC/MCFragment.h
The file was modifiedllvm/lib/MC/MCFragment.cpp
Commit b9780f4f80ba82c6271b6b87fbfe6ea32d154e49 by qshanz
[DAGCombine] Don't check the legality of type when combine the
SIGN_EXTEND_INREG
This is the DAG node for SIGN_EXTEND_INREG :
t21: v4i32 = sign_extend_inreg t18, ValueType:ch:v4i16
It has two operands. The first one is the value it want to extend, and
the second one is the type to specify how to extend the value. For this
example, it means that, it is signed extend the t18(v4i32) from v4i16 to
v4i32. That is the semantics of c code:
vector int foo(vector int m) {
  return m << 16 >> 16;
}
And it could be any vector type that hardware support the operation,
though the type 'v4i16' is NOT legal for the target. When we are trying
to combine the srl + sra, what we did now is calling the
TLI.isOperationLegal(), which will also check the legality of the type.
That doesn't make sense.
Differential Revision: https://reviews.llvm.org/D70230
The file was modifiedllvm/test/CodeGen/PowerPC/sext-vector-inreg.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Commit 806a2b1f3d8850eb88f1f9338e86b6398841c961 by maskray
[MC] Reorder MCFragment members to decrease padding
sizeof(MCFragment) does not change, but some if its subclasses do, e.g.
on a 64-bit platform, sizeof(MCEncodedFragment) decreases from 64 to 56,
sizeof(MCDataFragment) decreases from 224 to 216.
The file was modifiedllvm/lib/MC/MCFragment.cpp
The file was modifiedllvm/include/llvm/MC/MCFragment.h