SuccessChanges

Changes from Git (git http://labmaster3.local/git/llvm-project.git)

Summary

  1. [clangd] Introduce bulletlists (details)
  2. [OPENMP]Do not diagnose references to non-integral types for ref in (details)
  3. [DAGCombiner] reduce shuffle of concat of same vector (details)
  4. [TypePromotion] Use SetVectors instead of PtrSets (details)
  5. [docs] NFC: Fix typos in documents (details)
  6. AMDGPU/GlobalISel: Partially fix llvm.amdgcn.kill pattern import (details)
  7. llc: Change behavior of -mcpu with existing attribute (details)
  8. OpaquePtr: print byval types containing anonymous types correctly. (details)
  9. AMDGPU/GlobalISel: Select llvm.amdgcn.wqm.vote (details)
Commit a000f2e53f5c3433608f6097c3f4096e313b5f56 by kadircet
[clangd] Introduce bulletlists
Reviewers: sammccall
Subscribers: ilya-biryukov, MaskRay, jkorous, arphaman, usaxena95,
cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D71422
The file was modifiedclang-tools-extra/clangd/FormattedString.h
The file was modifiedclang-tools-extra/clangd/unittests/FormattedStringTests.cpp
The file was modifiedclang-tools-extra/clangd/FormattedString.cpp
Commit 3f2e3dc44b42fab2e991222e74248b7006f1091e by a.bataev
[OPENMP]Do not diagnose references to non-integral types for ref in
declare simd.
According to the standard, a list-item that appears in a linear clause
without the ref modifier must be of integral or pointer type, or must be
a reference to an integral or pointer type. Added check that this
restriction is applied only to non-ref items.
The file was modifiedclang/lib/Sema/SemaOpenMP.cpp
The file was modifiedclang/test/OpenMP/declare_simd_messages.cpp
Commit 58e2e92a57fcc3c628fd03ae33698fcc9aabedb9 by spatel
[DAGCombiner] reduce shuffle of concat of same vector
This is possibly a small part towards solving PR42024:
https://bugs.llvm.org/show_bug.cgi?id=42024
The vectorizer is creating shuffles of concat like this:
%63 = shufflevector <4 x i64> %x, <4 x i64> undef, <8 x i32> <i32 0, i32
1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
%64 = shufflevector <8 x i64> %63, <8 x i64> undef, <8 x i32> <i32 0,
i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
That might be fixable in the vectorizers, but we're not allowed to fold
that into a single shuffle in instcombine, so we should have a backend
backstop to convert that into the likely simpler form:
%64 = shufflevector <4 x i64> %x, <4 x i64> undef, <8 x i32> <i32 0, i32
0, i32 1, i32 1, i32 2, i32 2, i32 3, i32 3>
Differential Revision: https://reviews.llvm.org/D72300
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-combining-avx.ll
Commit 3c7f740f284274636db72fb84e563bd5b55c8eb8 by sam.parker
[TypePromotion] Use SetVectors instead of PtrSets
Remove the chance of non-deterministic insertion of zexts of the sources
by using a SetVector instead of SmallPtrSet. Do the same for sinks for
consistency and to negate the small issue from possibly happening. The
SafeWrap instructions are now also stored in a SmallVector. The
IRPromoter members of these structures have been changed to references.
Differential Revision: https://reviews.llvm.org/D72322
The file was modifiedllvm/lib/CodeGen/TypePromotion.cpp
Commit e334a3a60f1161e11191ddcc1ba2b16b08db03bd by hans
[docs] NFC: Fix typos in documents
"the the" -> "the"
"an" -> "a"
Patch by Kazuaki Ishizaki <ishizaki@jp.ibm.com>!
Differential revision: https://reviews.llvm.org/D72091
The file was modifiedllvm/docs/ORCv2.rst
The file was modifiedllvm/docs/Frontend/PerformanceTips.rst
The file was modifiedllvm/docs/LangRef.rst
The file was modifiedllvm/docs/Atomics.rst
The file was modifiedllvm/docs/SourceLevelDebugging.rst
The file was modifiedllvm/docs/GlobalISel/GenericOpcode.rst
The file was modifiedllvm/docs/HowToBuildWithPGO.rst
The file was modifiedllvm/docs/Passes.rst
The file was modifiedllvm/docs/AMDGPUUsage.rst
Commit a428386d4a805f94299e5013805ddd4a2114f5f5 by arsenm2
AMDGPU/GlobalISel: Partially fix llvm.amdgcn.kill pattern import
Tests deferred since the existing DAG test depends on some other
operations, but isn't far from working as-is.
The file was modifiedllvm/lib/Target/AMDGPU/SIInstructions.td
Commit f26ed6e47cb8b080c236d11c4942a12265180084 by arsenm2
llc: Change behavior of -mcpu with existing attribute
Don't overwrite existing target-cpu attributes.
I've often found the replacement behavior annoying, and this is
inconsistent with how the fast math command line flags interact with the
function attributes.
Does not yet change target-features, since I think that should behave as
a concatenation.
The file was modifiedllvm/test/CodeGen/X86/avoid-sfb.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/memory-legalizer-atomic-insert-end.mir
The file was modifiedllvm/test/CodeGen/X86/avoid-sfb-overlaps.ll
The file was modifiedllvm/test/DebugInfo/COFF/inlining-files.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/X86/tail_folding_and_assume_safety.ll
The file was modifiedllvm/test/DebugInfo/COFF/inlining-header.ll
The file was modifiedllvm/test/Other/opt-override-mcpu-mattr.ll
The file was modifiedllvm/test/CodeGen/MIR/AMDGPU/llc-target-cpu-attr-from-cmdline-ir.mir
The file was modifiedllvm/test/tools/llvm-objdump/AMDGPU/source-lines.ll
The file was modifiedllvm/include/llvm/CodeGen/CommandFlags.inc
The file was modifiedllvm/test/CodeGen/X86/llc-override-mcpu-mattr.ll
Commit e130eef58814d12b0490033fbedcf75db8a4f148 by Tim Northover
OpaquePtr: print byval types containing anonymous types correctly.
Attribute::getAsString doesn't have enough information to print
anonymous Module-level types correctly, so they come back as "%type
0xabcd". This results in broken IR when printing as text.
Instead, print type-attributes (currently just byval) using the
TypePrinting infrastructure available in AsmWriter. This only applies to
function argument attributes.
The file was modifiedllvm/lib/IR/AsmWriter.cpp
The file was modifiedllvm/test/Assembler/byval-type-attr.ll
Commit 9150d6bd738a3d68ee1597751a874913e04b49d8 by arsenm2
AMDGPU/GlobalISel: Select llvm.amdgcn.wqm.vote
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.vote.ll
The file was modifiedllvm/lib/Target/AMDGPU/SOPInstructions.td
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wqm.vote.ll