SuccessChanges

Changes from Git (git http://labmaster3.local/git/llvm-project.git)

Summary

  1. AMDGPU/GlobalISel: Fix import of s_abs_i32 pattern (details)
  2. [InstCombine] try to pull 'not' of select into compare operands (details)
  3. Remove extraneous spaces (details)
  4. AMDGPU/GlobalISel: Fix readfirstlane pattern import (details)
  5. [ARM][MVE] Renamed VPT Block tests and files to something more (details)
  6. [HIP] Add option --gpu-max-threads-per-block=n (details)
  7. [AIX][XCOFF]Implement mergeable const (details)
  8. [LifetimeAnalysis] Do not forbid void deref type in (details)
  9. [analyzer] Update help text to reflect sarif support (details)
  10. [X86] Pull out repeated SrcVT.getVectorNumElements() call. NFCI. (details)
  11. [ARM] Regenerate bfi.ll test cases (details)
  12. [lldb] Initialize some bitfields in FuncUnwinders.cpp (details)
Commit e699c03c9be4839f03dcc3a7fa86a44594e80dcf by arsenm2
AMDGPU/GlobalISel: Fix import of s_abs_i32 pattern
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-abs.mir
The file was modifiedllvm/lib/Target/AMDGPU/SOPInstructions.td
Commit f8962571f70ad955d2da40b470a7cd246f19db23 by spatel
[InstCombine] try to pull 'not' of select into compare operands
not (select ?, (cmp TPred, ?, ?), (cmp FPred, ?, ?) -->
    select ?, (cmp TPred', ?, ?), (cmp FPred', ?, ?)
If both sides of the select are cmps, we can remove an instruction. The
case where only side is a cmp is deferred to a possible follow-on patch.
We have a more general 'isFreeToInvert' analysis, but I'm not seeing a
way to use that more widely without inducing infinite looping
(opposing transforms). Here, we flip the compare predicates directly, so
we should not have any danger by creating extra intermediate 'not' ops.
Alive proofs: https://rise4fun.com/Alive/jKa
Name: both select values are compares - invert predicates
%tcmp = icmp sle i32 %x, %y
%fcmp = icmp ugt i32 %z, %w
%sel = select i1 %cond, i1 %tcmp, i1 %fcmp
%not = xor i1 %sel, true
=>
%tcmp_not = icmp sgt i32 %x, %y
%fcmp_not = icmp ule i32 %z, %w
%not = select i1 %cond, i1 %tcmp_not, i1 %fcmp_not
Name: false val is compare - invert/not
%fcmp = icmp ugt i32 %z, %w
%sel = select i1 %cond, i1 %tcmp, i1 %fcmp
%not = xor i1 %sel, true
=>
%tcmp_not = xor i1 %tcmp, -1
%fcmp_not = icmp ule i32 %z, %w
%not = select i1 %cond, i1 %tcmp_not, i1 %fcmp_not
Differential Revision: https://reviews.llvm.org/D72007
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
The file was modifiedllvm/test/Transforms/InstCombine/not.ll
Commit 9daa44c9935053508b38d0203ac47130c8156b02 by medismail.bennani
Remove extraneous spaces
Signed-off-by: Med Ismail Bennani <medismail.bennani@gmail.com>
The file was modifiedlldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCRuntimeV2.cpp
Commit 78b30a54c97882740d5b12a85247bf1d2e86f0e2 by arsenm2
AMDGPU/GlobalISel: Fix readfirstlane pattern import
The imm folding optimization pattern failed to import. The instruction
pattern was already working, but failing to fail on SGPR inputs.
The file was modifiedllvm/lib/Target/AMDGPU/SIInstructions.td
The file was modifiedllvm/lib/Target/AMDGPU/VOP1Instructions.td
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.readfirstlane.mir
Commit ee811808a9a0e16a1b48d70cbe5d95525733d347 by sjoerd.meijer
[ARM][MVE] Renamed VPT Block tests and files to something more
informative. NFC
The file was removedllvm/test/CodeGen/Thumb2/mve-vpt-block7.mir
The file was addedllvm/test/CodeGen/Thumb2/mve-vpt-2-blocks.mir
The file was addedllvm/test/CodeGen/Thumb2/mve-vpt-block-1-ins.mir
The file was addedllvm/test/CodeGen/Thumb2/mve-vpt-block-2-ins.mir
The file was removedllvm/test/CodeGen/Thumb2/mve-vpt-block2.mir
The file was removedllvm/test/CodeGen/Thumb2/mve-vpt-block4.mir
The file was removedllvm/test/CodeGen/Thumb2/mve-vpt-block8.mir
The file was addedllvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-non-consecutive-ins.mir
The file was removedllvm/test/CodeGen/Thumb2/mve-vpt-block6.mir
The file was addedllvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-ctrl-flow.mir
The file was removedllvm/test/CodeGen/Thumb2/mve-vpt-block5.mir
The file was addedllvm/test/CodeGen/Thumb2/mve-vpt-3-blocks-kill-vpr.mir
The file was addedllvm/test/CodeGen/Thumb2/mve-vpt-block-4-ins.mir
The file was removedllvm/test/CodeGen/Thumb2/mve-vpt-block3.mir
The file was addedllvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-2-preds.mir
The file was removedllvm/test/CodeGen/Thumb2/mve-vpt-block.mir
Commit 9f2d8b5c0cdb31c5617476575c03826274ecbd25 by Yaxun.Liu
[HIP] Add option --gpu-max-threads-per-block=n
Add this option to change the default launch bounds.
Differential Revision: https://reviews.llvm.org/D71221
The file was modifiedclang/include/clang/Driver/Options.td
The file was modifiedclang/lib/Driver/ToolChains/HIP.cpp
The file was modifiedclang/lib/Frontend/CompilerInvocation.cpp
The file was modifiedclang/include/clang/Basic/LangOptions.def
The file was addedclang/test/Driver/hip-options.hip
The file was modifiedclang/test/CodeGenCUDA/amdgpu-kernel-attrs.cu
The file was modifiedclang/lib/CodeGen/TargetInfo.cpp
Commit a3832f33d9323a5080321ca52321efd9c5741b63 by diggerlin
[AIX][XCOFF]Implement mergeable const
SUMMARY: In this patch, we map mergeable const objects to the read-only
section in the same manner as const objects that are not mergeable.
Reviewers: hubert.reinterpretcast,jasonliu Subscribers: wuzish,
nemanjai, hiraditya
Differential Revision: https://reviews.llvm.org/D71551
The file was modifiedllvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
The file was modifiedllvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
The file was addedllvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-const.ll
Commit 247a6032549efb03c14b79c035a47c660b75263e by xazax
[LifetimeAnalysis] Do not forbid void deref type in
gsl::Pointer/gsl::Owner annotations
It turns out it is useful to be able to define the deref type as void.
In case we have a type erased owner, we want to express that the pointee
can be basically any type. It should not be unnatural to have a void
deref type as we already familiar with "pointers to void".
Differential Revision: https://reviews.llvm.org/D72097
The file was modifiedclang/include/clang/Basic/DiagnosticSemaKinds.td
The file was modifiedclang/include/clang/Basic/AttrDocs.td
The file was modifiedclang/lib/Sema/SemaDeclAttr.cpp
The file was modifiedclang/test/SemaCXX/attr-gsl-owner-pointer.cpp
Commit 46ac6a4dcd9b629188b75fafbe04008c24d1fb55 by xazax
[analyzer] Update help text to reflect sarif support
Differential Revision: https://reviews.llvm.org/D72289
The file was modifiedclang/include/clang/Driver/Options.td
Commit 0e912e22b63d413a27596fc4457aec8a0a1af45c by llvm-dev
[X86] Pull out repeated SrcVT.getVectorNumElements() call. NFCI.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit 55de6fc0b66b943c16fa36328859c210c13c2321 by llvm-dev
[ARM] Regenerate bfi.ll test cases
The file was modifiedllvm/test/CodeGen/ARM/bfi.ll
Commit 57835d0198418ca6e397f4b0a50dc6057d93c04c by pavel
[lldb] Initialize some bitfields in FuncUnwinders.cpp
This got flagged by msan.
The file was modifiedlldb/source/Symbol/FuncUnwinders.cpp