SuccessChanges

Changes from Git (git http://labmaster3.local/git/llvm-project.git)

Summary

  1. [PowerPC] The VK_PLT symbolref modifier is only used on 32-bit ELF. (details)
  2. [X86] AMD Znver2 (Rome) Scheduler enablement (details)
  3. [ms] [X86] Use "P" modifier on all branch-target operands in inline X86 (details)
  4. [clang] Enforce triple in mempcpy test (details)
  5. [GlobalISel][AArch64] Import + select LDR*roW and STR*roW patterns (details)
  6. [X86] Add ueq/one fp128 quiet compare tests. NFC (details)
Commit 1a1dbea24df51e441f3517abb8e251df0029dad7 by sd.fertile
[PowerPC] The VK_PLT symbolref modifier is only used on 32-bit ELF.
[NFC]
Fix a conditional that guarded code for execution only on 32-bit ELF by
checking that the Subtarget was not 64-bit and not-Darwin. By adding a
new target ABI (AIX), the condition is no longer correct. This code is
dead for AIX, due to a 'report_fatal_error' for thread local storage
usage earlier in the pipeline, but needs to be modifed as part of
Darwins removal from the PowerPC backend.
The file was modifiedllvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
Commit 3408940f736955402b7676e3b8bab6906cc82637 by Ganesh.Gopalasubramanian
[X86] AMD Znver2 (Rome) Scheduler enablement
The patch gives out the details of the znver2 scheduler model. There are
few improvements with respect to execution units, latencies and
throughput when compared with znver1. The tests that were present for
znver1 for llvm-mca tool were replicated. The latencies, execution
units, timeline and throughput information are updated for znver2.
Reviewers: craig.topper, Simon Pilgrim
Differential Revision: https://reviews.llvm.org/D66088
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-sse1.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-rdseed.s
The file was modifiedllvm/lib/Target/X86/X86InstrInfo.td
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-x86_64.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-f16c.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-cmov.s
The file was modifiedllvm/test/tools/llvm-mca/X86/scheduler-queue-usage.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/partial-reg-update-3.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-avx1.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-sse42.s
The file was modifiedllvm/test/tools/llvm-mca/X86/fma3-read-after-ld-2.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-sse41.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/partial-reg-update-6.s
The file was modifiedllvm/test/MC/X86/x86_long_nop.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-rdrand.s
The file was modifiedllvm/test/tools/llvm-mca/X86/variable-blend-read-after-ld-2.s
The file was modifiedllvm/test/tools/llvm-mca/X86/fma3-read-after-ld-1.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-bmi1.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-sse2.s
The file was modifiedllvm/test/tools/llvm-mca/X86/register-file-statistics.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/partial-reg-update-4.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-mwaitx.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-lea.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/partial-reg-update.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-bmi2.s
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver1/resources-clzero.s
The file was modifiedllvm/test/tools/llvm-mca/X86/variable-blend-read-after-ld-1.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-clflushopt.s
The file was modifiedllvm/test/tools/llvm-mca/X86/read-after-ld-2.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-fma.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-pclmul.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/partial-reg-update-5.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/partial-reg-update-2.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-popcnt.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-avx2.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-x86_32.s
The file was modifiedllvm/lib/Target/X86/X86.td
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-sse4a.s
The file was modifiedllvm/test/tools/llvm-mca/X86/cpus.s
The file was modifiedllvm/test/tools/llvm-mca/X86/bzhi-read-after-ld.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-ssse3.s
The file was modifiedllvm/test/tools/llvm-mca/X86/read-after-ld-1.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-prefetchw.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-adx.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-movbe.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-sha.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-mmx.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-clzero.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-aes.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-sse3.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/partial-reg-update-7.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-cmpxchg.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-fsgsbase.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-x87.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-lzcnt.s
The file was modifiedllvm/test/tools/llvm-mca/X86/sqrt-rsqrt-rcp-memop.s
The file was addedllvm/lib/Target/X86/X86ScheduleZnver2.td
The file was modifiedllvm/test/tools/llvm-mca/X86/Generic/resources-clzero.s
The file was modifiedllvm/test/tools/llvm-mca/X86/bextr-read-after-ld.s
Commit 1c545f6dbcbb3ada2dfef2c6afbc1ca8939135cb by epastor
[ms] [X86] Use "P" modifier on all branch-target operands in inline X86
assembly.
Summary: Extend D71677 to apply to all branch-target operands, rather
than special-casing call instructions.
Also add a regression test for llvm.org/PR44272, since this finishes
fixing it.
Reviewers: thakis, rnk
Reviewed By: thakis
Subscribers: merge_guards_bot, hiraditya, cfe-commits, llvm-commits
Tags: #clang, #llvm
Differential Revision: https://reviews.llvm.org/D72417
The file was modifiedllvm/include/llvm/MC/MCParser/MCParsedAsmOperand.h
The file was modifiedclang/test/CodeGen/ms-inline-asm-64.c
The file was modifiedllvm/lib/MC/MCParser/AsmParser.cpp
The file was modifiedllvm/lib/Target/X86/X86InstrControl.td
The file was modifiedllvm/lib/Target/X86/AsmParser/X86Operand.h
The file was modifiedllvm/lib/Target/X86/X86InstrInfo.td
The file was modifiedllvm/utils/TableGen/X86RecognizableInstr.cpp
The file was modifiedllvm/include/llvm/MC/MCInstrDesc.h
The file was modifiedllvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
The file was modifiedllvm/utils/TableGen/InstrInfoEmitter.cpp
Commit b35f5d4914c979282010c0618a331d11a58493ac by sguelton
[clang] Enforce triple in mempcpy test
Fixes
http://lab.llvm.org:8011/builders/llvm-clang-win-x-armv7l/builds/2597
The file was modifiedclang/test/CodeGen/mempcpy-libcall.c
Commit 9949b1a1753aa0f229c5b55ea01ec96f48164d9e by Jessica Paquette
[GlobalISel][AArch64] Import + select LDR*roW and STR*roW patterns
This adds support for selecting a large chunk of the load/store *roW
patterns.
This is pretty much a straight port of
AArch64DAGToDAGISel::SelectAddrModeWRO into GISel. The code is very
similar to the XRO code. The main difference is that in the *roW
patterns, we want to try and fold in an extend, and *possibly* a shift
along with it. A good portion of this patch is refactoring the existing
XRO code.
- Add selectAddrModeWRO
- Factor out the code from selectAddrModeShiftedExtendXReg which is used
by both
selectAddrModeXRO and selectAddrModeWRO into selectExtendedSHL.
This is similar to the function of the same name in
AArch64DAGToDAGISel.
- Add support for extends to the factored out code in selectExtendedSHL.
- Teach getExtendTypeForInst how to handle AND masks that are intended
to be
used in loads/stores (necessary for this addressing mode.)
- Make getExtendTypeForInst not static because moving it made an
annoying diff
and I wanted to have the WRO/XRO functions close to each other while I
was
writing the code.
Differential Revision: https://reviews.llvm.org/D72426
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/store-wro-addressing-modes.mir
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/load-wro-addressing-modes.mir
The file was modifiedllvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrFormats.td
Commit 4e003aad42d985dade66cd5928d64dd09edecceb by craig.topper
[X86] Add ueq/one fp128 quiet compare tests. NFC
The ONE expansion calls OGT/OLT libcalls which will signal for QNAN. The
UEQ expansion uses unord and eq libcalls which won't signal. We should
probably use those libcalls for ONE with appropriate logic.
Quiet OGT/OLT/OLE/OGE have similar issue, but not sure how to fix those
yet.
The file was modifiedllvm/test/CodeGen/X86/fp128-libcalls-strict.ll
The file was modifiedllvm/test/CodeGen/X86/fp128-compare.ll