SuccessChanges

Changes from Git (git http://labmaster3.local/git/llvm-project.git)

Summary

  1. [TableGen] Introduce a `defvar` statement. (details)
  2. [TableGen] Introduce an if/then/else statement. (details)
  3. [Target] Fix uninitialized value in (details)
  4. [ARM][MVE] Masked gathers from base + vector of offsets (details)
  5. [mlir] Add loop.parallel, loop.reduce and loop.reduce.return operations. (details)
  6. [mlir] Ran git-clang-format. (details)
  7. [lldb][NFC] Cleanup ClangASTContext::CompleteTagDeclarationDefinition (details)
  8. [mlir] Create a gpu.module operation for the GPU Dialect. (details)
  9. [RISCV] Fix ILP32D lowering for double+double/double+int return types (details)
  10. [mlir] Fix translation of splat constants to LLVM IR (details)
  11. [ARM][MVE] Disallow VPSEL for tail predication (details)
  12. [SelectionDAG] ComputeKnownBits - merge (details)
  13. [X86][SSE] Add add(shl(and(x,c1),c2),c3) test case with non-uniform (details)
  14. [ARM][Thumb2] Fix ADD/SUB invalid writes to SP (details)
  15. [ARM][LowOverheadLoops] Change predicate inspection (details)
  16. [SelectionDAG] ComputeKnownBits - merge (details)
  17. Fix "MIParser::getIRValue(unsigned int)’ defined but not used" warning. (details)
Commit 3388b0f59dcc7813278c753f96b66229f290cc59 by simon.tatham
[TableGen] Introduce a `defvar` statement.
Summary: This allows you to define a global or local variable to an
arbitrary value, and refer to it in subsequent definitions.
The main use I anticipate for this is if you have to compute some
difficult function of the parameters of a multiclass, and then use it
many times. For example:
  multiclass Foo<int i, string s> {
   defvar op = !cast<BaseClass>("whatnot_" # s # "_" # i);
   def myRecord {
     dag a = (op this, (op that, the other), (op x, y, z));
     int b = op.subfield;
   }
   def myOtherRecord<"template params including", op>;
}
There are a couple of ways to do this already, but they're not really
satisfactory. You can replace `defvar x = y` with a loop over a
singleton list, `foreach x = [y] in { ... }` - but that's unintuitive to
someone who hasn't seen that workaround idiom before, and requires an
extra pair of braces that you often didn't really want. Or you can
define a nested pair of multiclasses, with the inner one taking `x` as a
template parameter, and the outer one instantiating it just once with
the desired value of `x` computed from its other parameters - but that
makes it awkward to sequentially compute each value based on the
previous ones. I think `defvar` makes things considerably easier.
You can also use `defvar` at the top level, where it inserts globals
into the same map used by `defset`. That allows you to define global
constants without having to make a dummy record for them to live in:
  defvar MAX_BUFSIZE = 512;
  // previously:
// def Dummy { int MAX_BUFSIZE = 512; }
// and then refer to Dummy.MAX_BUFSIZE everywhere
Reviewers: nhaehnle, hfinkel
Reviewed By: hfinkel
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D71407
The file was modifiedllvm/lib/TableGen/TGParser.h
The file was modifiedllvm/docs/TableGen/LangRef.rst
The file was addedllvm/test/TableGen/defvar.td
The file was modifiedllvm/lib/TableGen/TGLexer.h
The file was modifiedllvm/lib/TableGen/TGLexer.cpp
The file was modifiedllvm/lib/TableGen/TGParser.cpp
Commit ddbc0b1e516407a24d986a1998026f1ac5864270 by simon.tatham
[TableGen] Introduce an if/then/else statement.
Summary: This allows you to make some of the defs in a multiclass or
`foreach` conditional on an expression computed from the parameters or
iteration variables.
It was already possible to simulate an if statement using a `foreach`
with a dummy iteration variable and a list constructed using `!if` so
that it had length 0 or 1 depending on the condition, e.g.
  foreach unusedIterationVar = !if(condition, [1], []<int>) in { ... }
But this syntax is nicer to read, and also more convenient because it
allows an else clause.
To avoid upheaval in the implementation, I've implemented `if` as pure
syntactic sugar on the `foreach` implementation: internally, `ParseIf`
actually does construct exactly the kind of foreach shown above (and
another reversed one for the else clause if present).
Reviewers: nhaehnle, hfinkel
Reviewed By: hfinkel
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D71474
The file was modifiedllvm/test/TableGen/defvar.td
The file was modifiedllvm/docs/TableGen/LangRef.rst
The file was modifiedllvm/lib/TableGen/TGLexer.cpp
The file was modifiedllvm/lib/TableGen/TGParser.cpp
The file was addedllvm/test/TableGen/ifstmt.td
The file was modifiedllvm/lib/TableGen/TGLexer.h
The file was modifiedllvm/lib/TableGen/TGParser.h
Commit 41b520188820a732e6de4865c08704f412013209 by sam.mccall
[Target] Fix uninitialized value in
10c11e4e2d05cf0e8f8251f50d84ce77eb1e9b8d
The file was modifiedllvm/include/llvm/Target/TargetOptions.h
Commit 72ca86fd34ecc5f7ccbaf923d2d508dad2a6a64c by anna.welker
[ARM][MVE] Masked gathers from base + vector of offsets
Enables the masked gather pass to create a masked gather loading from a
base and vector of offsets. This also enables v8i16 and v16i8 gather
loads.
Differential Revision: https://reviews.llvm.org/D72330
The file was modifiedllvm/test/CodeGen/Thumb2/mve-gather-ptrs.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-gather-ind32-unscaled.ll
The file was modifiedllvm/lib/Target/ARM/MVEGatherScatterLowering.cpp
The file was addedllvm/test/CodeGen/Thumb2/mve-gather-ind16-scaled.ll
The file was addedllvm/test/CodeGen/Thumb2/mve-gather-ind16-unscaled.ll
The file was addedllvm/test/CodeGen/Thumb2/mve-gather-ind8-unscaled.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-gather-ind32-scaled.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-gather-scatter-opt.ll
Commit 018b042593f007456b0695421942ec84ec816a30 by Adrian Prantl
[mlir] Add loop.parallel, loop.reduce and loop.reduce.return operations.
Summary: These operations can be used to specify a loop nest with a body
that can contain reductions. The iteration space can be iterated in any
order.
RFC:
https://groups.google.com/a/tensorflow.org/d/topic/mlir/pwtSgiKFPis/discussion
Differential Revision: https://reviews.llvm.org/D72394
The file was modifiedmlir/lib/Dialect/LoopOps/LoopOps.cpp
The file was modifiedmlir/test/Dialect/Loops/invalid.mlir
The file was modifiedmlir/include/mlir/Dialect/LoopOps/LoopOps.td
The file was modifiedmlir/test/Dialect/Loops/ops.mlir
Commit 5a6eae3dea2342c2a83e4502de43927808f8ca21 by Adrian Prantl
[mlir] Ran git-clang-format.
Summary: I forgot to ran git-clang-format before committing.
The file was modifiedmlir/lib/Dialect/LoopOps/LoopOps.cpp
Commit 9492e9d8cfd356109276da5aa926b297db0e16db by Raphael Isemann
[lldb][NFC] Cleanup ClangASTContext::CompleteTagDeclarationDefinition
Makes this function exit early instead of nesting if statements.
Also removed all the if (tag_type->getDecl()) checks. If we created a
TagType with a nullptr as a Decl then Clang would have already
deferenced that nullptr during TagType creation so there is no point in
gracefully handling a nullptr here.
The file was modifiedlldb/source/Symbol/ClangASTContext.cpp
Commit 4624a1e8ac8a3f69cc887403b976f538f587744a by herhut
[mlir] Create a gpu.module operation for the GPU Dialect.
Summary: This is based on the use of code constantly checking for an
attribute on a model and instead represents the distinct operaion with a
different op. Instead, this op can be used to provide better filtering.
Reviewers: herhut, mravishankar, antiagainst, rriddle
Reviewed By: herhut, antiagainst, rriddle
Subscribers: liufengdb, aartbik, jholewinski, mgorny, mehdi_amini,
rriddle, jpienaar, burmako, shauheen, antiagainst, nicolasvasilache,
csigg, arpith-jacob, mgester, lucyrfox, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D72336
The file was modifiedmlir/lib/Conversion/GPUToSPIRV/ConvertGPUToSPIRVPass.cpp
The file was modifiedmlir/lib/Conversion/GPUToCUDA/ConvertKernelFuncToCubin.cpp
The file was modifiedmlir/test/Dialect/GPU/invalid.mlir
The file was modifiedmlir/lib/Dialect/GPU/IR/GPUDialect.cpp
The file was modifiedmlir/include/mlir/Dialect/GPU/GPUOps.td
The file was modifiedmlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp
The file was modifiedmlir/lib/Dialect/GPU/Transforms/KernelOutlining.cpp
The file was modifiedmlir/include/mlir/Conversion/GPUToNVVM/GPUToNVVMPass.h
The file was modifiedmlir/lib/Conversion/GPUToCUDA/ConvertLaunchFuncToCudaCalls.cpp
The file was modifiedmlir/test/Conversion/GPUToNVVM/memory-attrbution.mlir
The file was modifiedmlir/lib/Conversion/GPUToSPIRV/ConvertGPUToSPIRV.cpp
The file was modifiedmlir/test/Conversion/GPUToSPIRV/simple.mlir
The file was modifiedmlir/tools/mlir-cuda-runner/mlir-cuda-runner.cpp
The file was addedmlir/lib/Conversion/GPUToSPIRV/GPUToSPIRV.td
The file was modifiedmlir/test/Conversion/GPUToSPIRV/builtins.mlir
The file was modifiedmlir/test/Conversion/GPUToNVVM/gpu-to-nvvm.mlir
The file was modifiedmlir/test/Conversion/GPUToSPIRV/load-store.mlir
The file was modifiedmlir/test/Dialect/GPU/ops.mlir
The file was modifiedmlir/include/mlir/Conversion/GPUToCUDA/GPUToCUDAPass.h
The file was modifiedmlir/test/Dialect/GPU/outlining.mlir
The file was modifiedmlir/test/Conversion/GPUToSPIRV/loop.mlir
The file was modifiedmlir/lib/Conversion/GPUToSPIRV/CMakeLists.txt
The file was modifiedmlir/test/Conversion/GPUToCUDA/lower-launch-func-to-cuda.mlir
The file was modifiedmlir/test/Conversion/GPUToCUDA/lower-nvvm-kernel-to-cubin.mlir
Commit 3d6c492d7a9830a1a39b85dfa215743581d52715 by jrtc27
[RISCV] Fix ILP32D lowering for double+double/double+int return types
Summary: Previously, since these aggregates are > 2*XLen, Clang would
think they were being returned indirectly and thus would decrease the
number of available GPRs available by 1. For long argument lists this
could lead to a struct argument incorrectly being passed indirectly.
Reviewers: asb, lenary
Reviewed By: asb, lenary
Subscribers: luismarques, rbar, johnrusso, simoncook, apazos, sabuasal,
niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01,
MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna,
Jim, lenary, s.egerton, pzheng, sameer.abuasal, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D69590
The file was modifiedclang/test/CodeGen/riscv32-ilp32d-abi.c
The file was modifiedclang/lib/CodeGen/TargetInfo.cpp
Commit d6ea8ff0d74bfe5cd181ccfe91c2c300c5f7a35d by zinenko
[mlir] Fix translation of splat constants to LLVM IR
Summary: When converting splat constants for nested sequential LLVM IR
types wrapped in MLIR, the constant conversion was erroneously assuming
it was always possible to recursively construct a constant of a
sequential type given only one value. Instead, wait until all sequential
types are unpacked recursively before constructing a scalar constant and
wrapping it into the surrounding sequential type.
Subscribers: mehdi_amini, rriddle, jpienaar, burmako, shauheen,
antiagainst, nicolasvasilache, arpith-jacob, mgester, lucyrfox, aartbik,
liufengdb, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D72688
The file was modifiedmlir/test/Target/llvmir.mlir
The file was modifiedmlir/lib/Target/LLVMIR/ModuleTranslation.cpp
Commit e73b20c57dc7a8c847ebadeb7e19c08ec84f5bd7 by sam.parker
[ARM][MVE] Disallow VPSEL for tail predication
Due to the current way that we collect predicated instructions, we can't
easily handle vpsel in tail predicated loops. There are a couple of
issues: 1) It will use the VPR as a predicate operand, but doesn't have
to be
  instead a VPT block, which means we can assert while building up
  the VPT block because we don't find another VPST to being a new
  one. 2) VPSEL still requires a VPR operand even after tail
predicating,
  which means we can't remove it unless there is another
  instruction, such as vcmp, that can provide the VPR def.
The first issue should be a relatively simple fix in the logic of the
LowOverheadLoops pass, whereas the second will require us to represent
the 'implicit' tail predication with an explicit value.
Differential Revision: https://reviews.llvm.org/D72629
The file was addedllvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpsel-1.mir
The file was modifiedllvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
The file was addedllvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-2.mir
The file was addedllvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-3.mir
The file was addedllvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpsel-2.mir
The file was modifiedllvm/lib/Target/ARM/ARMInstrMVE.td
The file was addedllvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-1.mir
Commit a43b0065c5c78eba3fb83881fb628f5b8182db64 by llvm-dev
[SelectionDAG] ComputeKnownBits - merge
getValidMinimumShiftAmountConstant() and generic ISD::SRL handling.
As mentioned by @nikic on rGef5debac4302 (although that was just about
SHL), we can merge the guaranteed top zero bits from the shifted value,
and then, if a min shift amount is known, zero out the top bits as well.
SHL tests / handling will be added in a follow up patch.
The file was modifiedllvm/test/CodeGen/X86/vector-idiv-udiv-256.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
The file was modifiedllvm/test/CodeGen/X86/vector-idiv-udiv-128.ll
Commit fd42a4ac7a69adb92f87c7fa927509f177dcc6ca by llvm-dev
[X86][SSE] Add add(shl(and(x,c1),c2),c3) test case with non-uniform
shift value
As mentioned by @nikic on rGef5debac4302, we should merge the guaranteed
top zero bits from the shifted value and min shift amount code so they
can both set the high bits to zero.
The file was modifiedllvm/test/CodeGen/X86/combine-shl.ll
Commit d94d079a6a5b12156e4b818c8ba46eb143f335b9 by diogo.sampaio
[ARM][Thumb2] Fix ADD/SUB invalid writes to SP
Summary: This patch fixes pr23772  [ARM] r226200 can emit illegal thumb2
instruction: "sub sp, r12, #80". The violation was that SUB and ADD
(reg, immediate) instructions can only write to SP if the source
register is also SP. So the above instructions was unpredictable. To
enforce that the instruction t2(ADD|SUB)ri does not write to SP we now
enforce the destination register to be rGPR (That exclude PC and SP).
Different than the ARM specification, that defines one instruction that
can read from SP, and one that can't, here we inserted one that can't
write to SP, and other that can only write to SP as to reuse most of the
hard-coded size optimizations. When performing this change, it uncovered
that emitting Thumb2 Reg plus Immediate could not emit all variants of
ADD SP, SP #imm instructions before so it was refactored to be able to.
(see test/CodeGen/Thumb2/mve-stacksplot.mir where we use a subw sp, sp,
Imm12 variant ) It also uncovered a disassembly issue of adr.w
instructions, that were only written as SUBW instructions (see
llvm/test/MC/Disassembler/ARM/thumb2.txt).
Reviewers: eli.friedman, dmgreen, carwil, olista01, efriedma, andreadb
Reviewed By: efriedma
Subscribers: gbedwell, john.brawn, efriedma, ostannard, kristof.beyls,
hiraditya, dmgreen, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D70680
The file was modifiedllvm/test/CodeGen/ARM/GlobalISel/thumb-select-load-store.mir
The file was modifiedllvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
The file was modifiedllvm/test/MC/ARM/basic-thumb2-instructions.s
The file was modifiedllvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
The file was modifiedllvm/test/MC/Disassembler/ARM/thumb2.txt
The file was modifiedllvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
The file was modifiedllvm/test/MC/ARM/negative-immediates.s
The file was modifiedllvm/test/MC/ARM/thumb-diagnostics.s
The file was modifiedllvm/lib/Target/ARM/ARMAsmPrinter.cpp
The file was modifiedllvm/test/CodeGen/Thumb2/fp16-stacksplot.mir
The file was modifiedllvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
The file was modifiedllvm/test/CodeGen/Thumb2/peephole-addsub.mir
The file was modifiedllvm/test/MC/ARM/register-token-source-loc.s
The file was modifiedllvm/test/CodeGen/Thumb2/peephole-cmp.mir
The file was modifiedllvm/lib/Target/ARM/Thumb2InstrInfo.cpp
The file was addedllvm/test/CodeGen/Thumb2/t2peephole-t2ADDrr-to-t2ADDri.ll
The file was modifiedllvm/test/MC/Disassembler/ARM/invalid-thumbv7.txt
The file was modifiedllvm/test/MC/Disassembler/ARM/thumb-tests.txt
The file was modifiedllvm/test/CodeGen/MIR/ARM/thumb2-sub-sp-t3.mir
The file was modifiedllvm/test/CodeGen/ARM/GlobalISel/thumb-select-arithmetic-ops.mir
The file was modifiedllvm/test/MC/ARM/invalid-addsub.s
The file was addedllvm/test/tools/llvm-mca/ARM/simple-cortex-m33.s
The file was modifiedllvm/lib/Target/ARM/ARMInstrThumb2.td
The file was modifiedllvm/test/CodeGen/Thumb2/mve-stacksplot.mir
The file was modifiedllvm/test/MC/Disassembler/ARM/thumb2-v8.txt
The file was addedllvm/test/CodeGen/Thumb2/bug-subw.ll
Commit bad6032bc15fa8d16b67b86ef2b2fe48724e756e by sam.parker
[ARM][LowOverheadLoops] Change predicate inspection
Use the already provided helper function to get the operand type so that
we can detect whether the vpr is being used as a predicate or not. Also
use existing helpers to get the predicate indices when we converting the
vpt blocks. This enables us to support both types of vpr predicate
operand.
Differential Revision: https://reviews.llvm.org/D72504
The file was modifiedllvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
The file was addedllvm/test/CodeGen/Thumb2/LowOverheadLoops/vmaxmin_vpred_r.mir
Commit c05a11108b9a9deb266c3c1758677462df61e05e by llvm-dev
[SelectionDAG] ComputeKnownBits - merge
getValidMinimumShiftAmountConstant() and generic ISD::SHL handling.
As mentioned by @nikic on rGef5debac4302, we can merge the guaranteed
bottom zero bits from the shifted value, and then, if a min shift amount
is known, zero out the bottom bits as well.
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
The file was modifiedllvm/test/CodeGen/X86/combine-shl.ll
Commit 31aed2e0dad25d43039a9b933b1b95fbdeb27704 by llvm-dev
Fix "MIParser::getIRValue(unsigned int)’ defined but not used" warning.
NFCI.
The file was modifiedllvm/lib/CodeGen/MIRParser/MIParser.cpp