SuccessChanges

Changes from Git (git http://labmaster3.local/git/llvm-project.git)

Summary

  1. [AMDGPU] Invert the handling of skip insertion. (details)
  2. [MachO] Add a test for detecting reserved unit length. (details)
  3. [gn build] Port 0dc6c249bff (details)
  4. [DWARF] Fix DWARFDebugAranges to support 64-bit CU offsets. (details)
  5. [RISCV] Support ABI checking with per function target-features (details)
Commit 0dc6c249bffac9f23a605ce4e42a84341da3ddbd by cdevadas
[AMDGPU] Invert the handling of skip insertion.
The current implementation of skip insertion (SIInsertSkip) makes it a
mandatory pass required for correctness. Initially, the idea was to have
an optional pass. This patch inserts the s_cbranch_execz upfront during
SILowerControlFlow to skip over the sections of code when no lanes are
active. Later, SIRemoveShortExecBranches removes the skips for short
branches, unless there is a sideeffect and the skip branch is really
necessary.
This new pass will replace the handling of skip insertion in the
existing SIInsertSkip Pass.
Differential revision: https://reviews.llvm.org/D68092
The file was modifiedllvm/test/CodeGen/AMDGPU/smrd_vmem_war.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/insert-skips-gws.mir
The file was modifiedllvm/lib/Target/AMDGPU/CMakeLists.txt
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/ret_jump.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/wave32.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/branch-condition-and.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIInsertSkips.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/call-skip.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/si-lower-control-flow-unreachable-block.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/else.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/skip-if-dead.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/si-annotate-cf-noloop.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/uniform-cfg.ll
The file was addedllvm/lib/Target/AMDGPU/SIRemoveShortExecBranches.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/atomic_optimizations_pixelshader.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/hoist-cond.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/cse-phi-incoming-val.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPU.h
The file was modifiedllvm/test/CodeGen/AMDGPU/skip-branch-taildup-ret.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/insert-skips-kill-uncond.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/skip-branch-trap.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/convergent-inlineasm.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/valu-i1.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/uniform-loop-inside-nonuniform.ll
The file was modifiedllvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/wqm.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/collapse-endcf.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/insert-skips-flat-vmem.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/insert-skips-ignored-insts.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/branch-relaxation.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/si-lower-control-flow.mir
Commit fcc08aa835de1e0c1f3e7e479917575e55433b68 by ikudrin
[MachO] Add a test for detecting reserved unit length.
This is a follow-up for D71546 to add a corresponding unit test.
Differential Revision: https://reviews.llvm.org/D72695
The file was modifiedlld/unittests/MachOTests/MachONormalizedFileToAtomsTests.cpp
Commit 4b1d471fa61f2d390d4dd5f2e95862a3cb5a6ec0 by llvmgnsyncbot
[gn build] Port 0dc6c249bff
The file was modifiedllvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn
Commit 2142e20f50954b9b5085e9b9461efc318a3348c0 by ikudrin
[DWARF] Fix DWARFDebugAranges to support 64-bit CU offsets.
DWARFContext, the only user of this class, can already handle such
offsets.
Differential Revision: https://reviews.llvm.org/D71834
The file was modifiedllvm/include/llvm/DebugInfo/DWARF/DWARFDebugAranges.h
The file was modifiedllvm/lib/DebugInfo/DWARF/DWARFDebugAranges.cpp
Commit 109e4d12edda07bdec139de36d9fdb6f73399f92 by zakk.chen
[RISCV] Support ABI checking with per function target-features
if users don't specific -mattr, the default target-feature come from IR
attribute.
The file was modifiedllvm/test/CodeGen/RISCV/subtarget-features-std-ext.ll
The file was modifiedllvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
The file was modifiedllvm/lib/Target/RISCV/Utils/RISCVBaseInfo.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp