SuccessChanges

Changes from Git (git https://github.com/llvm/llvm-project.git)

Summary

  1. [ARM] Follow AACPS standard for volatile bit-fields access width (details)
  2. [GVN] Add testcase that uses masked loads and stores, NFC (details)
  3. Add more explicit error message when creating a type or attribute for an unregistered dialect (NFC) (details)
Commit 514df1b2bb1ecd1a33327001ea38a347fd2d0380 by ties.stuij
[ARM] Follow AACPS standard for volatile bit-fields access width

This patch resumes the work of D16586.
According to the AAPCS, volatile bit-fields should
be accessed using containers of the widht of their
declarative type. In such case:
```
struct S1 {
  short a : 1;
}
```
should be accessed using load and stores of the width
(sizeof(short)), where now the compiler does only load
the minimum required width (char in this case).
However, as discussed in D16586,
that could overwrite non-volatile bit-fields, which
conflicted with C and C++ object models by creating
data race conditions that are not part of the bit-field,
e.g.
```
struct S2 {
  short a;
  int  b : 16;
}
```
Accessing `S2.b` would also access `S2.a`.

The AAPCS Release 2020Q2
(https://documentation-service.arm.com/static/5efb7fbedbdee951c1ccf186?token=)
section 8.1 Data Types, page 36, "Volatile bit-fields -
preserving number and width of container accesses" has been
updated to avoid conflict with the C++ Memory Model.
Now it reads in the note:
```
This ABI does not place any restrictions on the access widths of bit-fields where the container
overlaps with a non-bit-field member or where the container overlaps with any zero length bit-field
placed between two other bit-fields. This is because the C/C++ memory model defines these as being
separate memory locations, which can be accessed by two threads simultaneously. For this reason,
compilers must be permitted to use a narrower memory access width (including splitting the access into
multiple instructions) to avoid writing to a different memory location. For example, in
struct S { int a:24; char b; }; a write to a must not also write to the location occupied by b, this requires at least two
memory accesses in all current Arm architectures. In the same way, in struct S { int a:24; int:0; int b:8; };,
writes to a or b must not overwrite each other.
```

Patch D16586 was updated to follow such behavior by verifying that we
only change volatile bit-field access when:
- it won't overlap with any other non-bit-field member
- we only access memory inside the bounds of the record
- avoid overlapping zero-length bit-fields.

Regarding the number of memory accesses, that should be preserved, that will
be implemented by D67399.

Differential Revision: https://reviews.llvm.org/D72932

The following people contributed to this patch:
- Diogo Sampaio
- Ties Stuij
The file was modifiedclang/include/clang/Basic/CodeGenOptions.def
The file was modifiedclang/test/CodeGen/aapcs-bitfield.c
The file was modifiedclang/lib/CodeGen/CGRecordLayoutBuilder.cpp
The file was modifiedclang/include/clang/Driver/Options.td
The file was modifiedclang/test/CodeGen/bitfield-2.c
The file was modifiedclang/lib/Frontend/CompilerInvocation.cpp
The file was modifiedclang/lib/CodeGen/CGExpr.cpp
The file was modifiedclang/lib/CodeGen/CGRecordLayout.h
Commit d0ccfcb040c684e91d8b5fe5111ba7f4ec7e019a by kparzysz
[GVN] Add testcase that uses masked loads and stores, NFC
The file was addedllvm/test/Transforms/GVN/masked-load-store.ll
Commit 97e77ac0ed80877cda58b1dddf98890cc7b0d167 by joker.eph
Add more explicit error message when creating a type or attribute for an unregistered dialect (NFC)

Differential Revision: https://reviews.llvm.org/D87177
The file was modifiedmlir/include/mlir/IR/AttributeSupport.h
The file was modifiedmlir/include/mlir/IR/TypeSupport.h
The file was modifiedmlir/include/mlir/Support/StorageUniquer.h
The file was modifiedmlir/lib/Support/StorageUniquer.cpp