FailedChanges

Summary

  1. Refactored getSingleBranchSchedulers, since now we use LLVMBuildFactory for all of the builders. (details)
  2. Got rid of legacy schedulers. (details)
Commit 993dd9a2b15d0dbfbad4c86377b8fca9cfed0852 by gkistanova
Refactored getSingleBranchSchedulers, since now we use LLVMBuildFactory for all of the builders.
The file was modifiedbuildbot/osuosl/master/config/schedulers.py (diff)
Commit 9c39add1f0c8aba6f5835466e72226890cc962cd by gkistanova
Got rid of legacy schedulers.
The file was modifiedbuildbot/osuosl/master/master.cfg (diff)

Summary

  1. [OpenMP] Fixed the issue that target memory deallocation might be called when they're being used (details)
  2. [ValueTracking] Improve llvm.abs handling in computeKnownBits. (details)
  3. Upgrade MC to v0.9. (details)
  4. Support experimental v extension v0.9. (details)
  5. [compiler-rt][Darwin] Fix linker errors for check-asan (details)
  6. [libc] [obvious] Fix strchr and strrchr tests so that constness is (details)
  7. [libc] [obvious] In strrchr, remove cast to unsigned char before (details)
  8. [X86] Simplify vpternlog immediate selection. (details)
  9. Don't crash if we deserialize a pack expansion type whose pattern (details)
  10. [AArch64][SVE] Allow vector of pointers as legal type for masked load/store. (details)
  11. [clang-tidy][NFC] Added convienence methods for getting optional options (details)
  12. [VE] Change calling convention to follow ABI (details)
  13. PowerPC: Fix SPE extloadf32 handling. (details)
  14. PowerPC: Don't lower SELECT_CC to PPCISD::FSEL on SPE (details)
  15. [X86] Use TargetLowering::getRegClassFor to simplify some code in tryVPTESTM. NFCI (details)
Commit f2400f024d323bc9000a4c126f2008a8b58fb4a0 by tianshilei1992
[OpenMP] Fixed the issue that target memory deallocation might be called when they're being used

This patch fixed the issue that target memory might be deallocated when
they're still being used or before they're used.

Reviewed By: ye-luo

Differential Revision: https://reviews.llvm.org/D84996
The file was modifiedopenmp/libomptarget/src/omptarget.cpp
Commit 86dea1f39bd127776b999e10dff212003068d30a by craig.topper
[ValueTracking] Improve llvm.abs handling in computeKnownBits.

Add the optimizations we have in the SelectionDAG version.
Known non-negative copies all known bits. Any known one other than
the sign bit makes result non-negative.

Differential Revision: https://reviews.llvm.org/D85000
The file was modifiedllvm/test/Transforms/InstCombine/abs-intrinsic.ll
The file was modifiedllvm/lib/Analysis/ValueTracking.cpp
Commit 47a4a27f47203055a4700b65533262409f83c491 by kai.wang
Upgrade MC to v0.9.

Differential revision: https://reviews.llvm.org/D80802
The file was addedllvm/test/MC/RISCV/rvv/ext.s
The file was modifiedllvm/test/MC/RISCV/rvv/snippet.s
The file was modifiedllvm/test/MC/RISCV/rvv/reduction.s
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfo.h
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrFormats.td
The file was modifiedllvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
The file was modifiedllvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
The file was modifiedllvm/test/MC/RISCV/rvv/fothers.s
The file was modifiedllvm/test/MC/RISCV/rvv/freduction.s
The file was modifiedllvm/test/MC/RISCV/rvv/mask.s
The file was modifiedllvm/test/MC/RISCV/rvv/load.s
The file was modifiedllvm/test/MC/RISCV/rvv/compare.s
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoV.td
The file was modifiedllvm/test/MC/RISCV/rvv/invalid.s
The file was modifiedllvm/test/MC/RISCV/rvv/fcompare.s
The file was modifiedllvm/test/MC/RISCV/rvv/store.s
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrFormatsV.td
The file was modifiedllvm/test/MC/RISCV/rvv/convert.s
The file was modifiedllvm/test/MC/RISCV/rvv/vsetvl.s
Commit 721d93fc5aa8c9f9fc9b86a9d3d1a58c6790213e by kai.wang
Support experimental v extension v0.9.

Differential revision: https://reviews.llvm.org/D81213
The file was modifiedclang/lib/Driver/ToolChains/Arch/RISCV.cpp
The file was modifiedclang/test/Driver/riscv-arch.c
Commit ff756f5231cc2ee9457129404e78420fa2791c7b by julian.lettner
[compiler-rt][Darwin] Fix linker errors for check-asan

A recent change broke `ninja check-asan` on Darwin by causing an error
during linking of ASan unit tests [1].

Move the addition of `-ObjC` compiler flag outside of the new
`if(COMPILER_RT_STANDALONE_BUILD)` block.  It doesn't add any global
flags (e.g, `${CMAKE_CXX_FLAGS}`) and the decision to add is based
solely on source paths (`${source_rpath}`).

[1] 8b2fcc42b895, https://reviews.llvm.org/D84466

Differential Revision: https://reviews.llvm.org/D85057
The file was modifiedcompiler-rt/cmake/Modules/CompilerRTCompile.cmake
Commit 5954755939febabcf1edb52b53214f25f06ce584 by gyurgyikcp
[libc] [obvious] Fix strchr and strrchr tests so that constness is
actually verified.
The file was modifiedlibc/test/src/string/strrchr_test.cpp
The file was modifiedlibc/test/src/string/strchr_test.cpp
Commit 1b35c4fed29d6136ce241a692ce0a7165e59bf81 by gyurgyikcp
[libc] [obvious] In strrchr, remove cast to unsigned char before
comparison.
The file was modifiedlibc/src/string/strrchr.cpp
Commit 93c678a79b0a8914954d77973593ea36706db5d5 by craig.topper
[X86] Simplify vpternlog immediate selection.

Rather than hardcoding immediate values for 12 different combinations
in a nested pair of switches, we can perform the matched logic
operation on 3 magic constants to calculate the immediate.

Special thanks to this tweet https://twitter.com/rygorous/status/1187034321992871936
for making me realize I could do this.
The file was modifiedllvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Commit 234f51a65a45b79402996ac6f0abcbb5793814bf by richard
Don't crash if we deserialize a pack expansion type whose pattern
contains no packs.

Fixes a regression from 740a164dec483225cbd02ab6c82199e2747ffacb.
The file was modifiedclang/test/PCH/cxx1y-lambdas.mm
The file was modifiedclang/test/PCH/cxx-variadic-templates.h
The file was modifiedclang/include/clang/AST/TypeProperties.td
The file was modifiedclang/test/PCH/cxx-variadic-templates.cpp
The file was modifiedclang/lib/AST/ASTImporter.cpp
The file was modifiedclang/test/PCH/cxx2a-constraints.cpp
Commit 01bfe2e494027e473ba920ef324b1929af16936e by huihuiz
[AArch64][SVE] Allow vector of pointers as legal type for masked load/store.

Refer to LangRef http://llvm.org/docs/LangRef.html#llvm-masked-load-intrinsics
'llvm.masked.load/store.*’ intrinsics are overloaded intrinsic, which allow the
load/store data to be a vector of any integer, floating-point or pointer data type.

Therefore, allow pointer data type when checking 'isLegalMaskedLoadStore()'.

Reviewed By: paulwalker-arm

Differential Revision: https://reviews.llvm.org/D85045
The file was modifiedllvm/test/CodeGen/AArch64/sve-masked-ldst-nonext.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
Commit 1fd2049e38daf0992f63883d68609b85dfb9cb26 by n.james93
[clang-tidy][NFC] Added convienence methods for getting optional options

These methods abstract away Error handling when trying to read options that can't be parsed by logging the error automatically and returning None.

Reviewed By: gribozavr2

Differential Revision: https://reviews.llvm.org/D84812
The file was modifiedclang-tools-extra/clang-tidy/ClangTidyCheck.cpp
The file was modifiedclang-tools-extra/clang-tidy/ClangTidyCheck.h
Commit 605fd4d77ce19c4d8c331732b490ef436ab093c2 by marukawa
[VE] Change calling convention to follow ABI

Change to expand all arguments and return values to i64 to follow ABI.
Update regression tests also.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D84581
The file was modifiedllvm/test/CodeGen/VE/int_to_fp.ll
The file was modifiedllvm/test/CodeGen/VE/or.ll
The file was modifiedllvm/test/CodeGen/VE/sext_zext_load.ll
The file was modifiedllvm/test/CodeGen/VE/va_caller.ll
The file was modifiedllvm/test/CodeGen/VE/setcci64.ll
The file was modifiedllvm/test/CodeGen/VE/pic_access_static_data.ll
The file was modifiedllvm/lib/Target/VE/VECallingConv.td
The file was modifiedllvm/test/CodeGen/VE/multiply.ll
The file was modifiedllvm/test/CodeGen/VE/setccf32i.ll
The file was modifiedllvm/test/CodeGen/VE/rotl.ll
The file was modifiedllvm/test/CodeGen/VE/xor.ll
The file was modifiedllvm/test/CodeGen/VE/load_off.ll
The file was modifiedllvm/test/CodeGen/VE/selectcci64c.ll
The file was modifiedllvm/test/CodeGen/VE/setccf64i.ll
The file was modifiedllvm/test/CodeGen/VE/setcci64i.ll
The file was modifiedllvm/test/CodeGen/VE/selectccf64c.ll
The file was modifiedllvm/test/CodeGen/VE/cast.ll
The file was modifiedllvm/test/CodeGen/VE/fp_to_int.ll
The file was modifiedllvm/test/CodeGen/VE/selectccf32c.ll
The file was modifiedllvm/test/CodeGen/VE/setcci32i.ll
The file was modifiedllvm/test/CodeGen/VE/setccf64.ll
The file was modifiedllvm/test/CodeGen/VE/max.ll
The file was modifiedllvm/test/CodeGen/VE/bswap.ll
The file was modifiedllvm/test/CodeGen/VE/selectcci32.ll
The file was modifiedllvm/test/CodeGen/VE/selectcci32i.ll
The file was modifiedllvm/test/CodeGen/VE/branch1.ll
The file was modifiedllvm/test/CodeGen/VE/addition.ll
The file was modifiedllvm/test/CodeGen/VE/left_shift.ll
The file was modifiedllvm/test/CodeGen/VE/cttz.ll
The file was modifiedllvm/test/CodeGen/VE/setccf32.ll
The file was modifiedllvm/test/CodeGen/VE/constants.ll
The file was modifiedllvm/test/CodeGen/VE/setcci32.ll
The file was modifiedllvm/test/CodeGen/VE/div.ll
The file was modifiedllvm/test/CodeGen/VE/selectcci32c.ll
The file was modifiedllvm/test/CodeGen/VE/select.ll
The file was modifiedllvm/test/CodeGen/VE/ctpop.ll
The file was modifiedllvm/test/CodeGen/VE/min.ll
The file was modifiedllvm/lib/Target/VE/VEISelLowering.cpp
The file was modifiedllvm/test/CodeGen/VE/nnd.ll
The file was modifiedllvm/test/CodeGen/VE/bitcast.ll
The file was modifiedllvm/test/CodeGen/VE/selectccf32i.ll
The file was modifiedllvm/test/CodeGen/VE/rem.ll
The file was modifiedllvm/test/CodeGen/VE/call.ll
The file was modifiedllvm/test/CodeGen/VE/rotr.ll
The file was modifiedllvm/test/CodeGen/VE/selectccf32.ll
The file was modifiedllvm/test/CodeGen/VE/ctlz.ll
The file was modifiedllvm/test/CodeGen/VE/right_shift.ll
The file was modifiedllvm/test/CodeGen/VE/bitreverse.ll
The file was modifiedllvm/test/CodeGen/VE/truncstore.ll
The file was modifiedllvm/test/CodeGen/VE/subtraction.ll
Commit 914dbf4808d46632cc7b8dda861a11f978083416 by jrh29
PowerPC: Fix SPE extloadf32 handling.

The patterns were incorrect copies from the FPU code, and are
unnecessary, since there's no extended load for SPE.  Just let LLVM
itself do the work by marking it expand.

Reviewed By: #powerpc, lkail
Differential Revision: https://reviews.llvm.org/D78670
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrSPE.td
The file was modifiedllvm/lib/Target/PowerPC/PPCISelLowering.cpp
The file was modifiedllvm/test/CodeGen/PowerPC/spe.ll
Commit 7e9153e940e21a937ff3a0e7425eb1b24bd1bb76 by jrh29
PowerPC: Don't lower SELECT_CC to PPCISD::FSEL on SPE

SPE doesn't have a fsel instruction, so don't try to lower to it.

This fixes a "Cannot select: tN: f64 = PPCISD::FSEL tX, tY, tZ" error.

Reviewed By: #powerpc, lkail
Differential Revision: https://reviews.llvm.org/D77773
The file was addedllvm/test/CodeGen/PowerPC/spe-fastmath.ll
The file was modifiedllvm/lib/Target/PowerPC/PPCISelLowering.cpp
Commit 1bd7046e4ce0102adef6096a12a289d7f94b8c73 by craig.topper
[X86] Use TargetLowering::getRegClassFor to simplify some code in tryVPTESTM. NFCI
The file was modifiedllvm/lib/Target/X86/X86ISelDAGToDAG.cpp

Summary

  1. Refactored getSingleBranchSchedulers, since now we use LLVMBuildFactory for all of the builders. (details)
  2. Got rid of legacy schedulers. (details)
Commit 993dd9a2b15d0dbfbad4c86377b8fca9cfed0852 by gkistanova
Refactored getSingleBranchSchedulers, since now we use LLVMBuildFactory for all of the builders.
The file was modifiedbuildbot/osuosl/master/config/schedulers.py
Commit 9c39add1f0c8aba6f5835466e72226890cc962cd by gkistanova
Got rid of legacy schedulers.
The file was modifiedbuildbot/osuosl/master/master.cfg