FailedChanges

Summary

  1. clang-x86-ninja-win10: removed DIA flag, added LIBZ flag (details)
Commit 3b3349e94a30eb9608e44f335ba74119311d714c by kuhnel
clang-x86-ninja-win10: removed DIA flag, added LIBZ flag
The file was modifiedbuildbot/osuosl/master/config/builders.py (diff)

Summary

  1. [AMDGPU] Generate test checks for splitkit-copy-bundle.mir (details)
  2. [SplitKit] Only copy live lanes (details)
  3. [NFC] EliminateDuplicatePHINodes(): small-size optimization: if there are <= 32 PHI's, O(n^2) algo is faster (geomean -0.08%) (details)
  4. Revert "Re-land: Add new hidden option -print-changed which only reports changes to IR" (details)
  5. [X86] Fix stack alignment on 32-bit Solaris/x86 (details)
  6. [lldb] Don't send invalid region addresses to lldb server (details)
  7. [clang][aarch64] ACLE: Support implicit casts between GNU and SVE vectors (details)
  8. [mlir][Linalg] Convolution tiling added to ConvOp vectorization pass (details)
  9. [AsmPrinter] Remove orphan DwarfUnit::shareAcrossDWOCUs declaration. NFCI. (details)
  10. [AMDGPU] Remove orphan SITargetLowering::LowerINT_TO_FP declaration. NFCI. (details)
  11. [AsmPrinter] DwarfDebug - use DebugLoc const references where possible. NFC. (details)
  12. [MLIR] Turns swapId into a FlatAffineConstraints member func (details)
  13. [gn build] (manually) port c9af34027bc (details)
  14. [mlir] turn clang-format back on in C API test (details)
  15. [ARM] Extra fp16 bitcast tests. NFC (details)
  16. DwarfFile.h - remove unnecessary includes. NFCI. (details)
  17. DwarfStringPool.cpp - remove unnecessary StringRef include. NFCI. (details)
  18. [ARM] Additional tests for qr intrinsics in loops. NFC (details)
  19. Revert "[lldb] Don't send invalid region addresses to lldb server" (details)
  20. [NFC][ARM] Tail fold test changes (details)
  21. SymbolizableObjectFile.h - remove unnecessary includes. NFCI. (details)
  22. MetadataLoader.cpp - remove unnecessary StringRef include. NFCI. (details)
  23. [clang-format][regression][PR47461] ifdef causes catch to be seen as a function (details)
  24. [ConstraintSystem] Remove local variable that is set but not read [NFC] (details)
  25. Remove unnecessary forward declarations. NFCI. (details)
  26. [clang][docs] Fix documentation of -O (details)
  27. [SLP] sort candidates to increase chance of optimal compare reduction (details)
  28. [llvm-readelf/obj][test] - Document what we print in various places for unnamed section symbols. (details)
  29. [obj2yaml] - Don't emit EM_NONE. (details)
  30. [SVE][CodeGen] Lower floating point -> integer conversions (details)
  31. [MemorySSA] Add another loop clobber test case. (details)
  32. [ARM][MachineOutliner] Add missing testcase for calls. (details)
  33. InstCombiner.h - remove unnecessary KnownBits.h include. NFCI. (details)
  34. [AMDGPU] Bump to ROCm 3.7 dependency hip_hcc->amdhip64 (details)
  35. SafeStackLayout.cpp - remove unnecessary StackLifetime.h include. NFCI. (details)
  36. [compiler-rt] Avoid pulling libatomic to sanitizer tests (details)
  37. ValueList.cpp - remove unnecessary includes. NFCI. (details)
  38. DwarfExpression.cpp - remove unnecessary includes. NFCI. (details)
  39. LiveDebugVariables.cpp - remove unnecessary Compiler.h include. NFCI. (details)
  40. [compiler-rt] Replace INLINE with inline (details)
  41. [compiler-rt] [tsan] [netbsd] Catch unsupported LONG_JMP_SP_ENV_SLOT (details)
  42. [AMDGPU] should expand ROTL i16 to shifts. (details)
  43. [compiler-rt] [netbsd] Include <sys/dkbad.h> (details)
  44. [compiler-rt] [hwasan] Replace INLINE with inline (details)
  45. [mlir][Standard] Canonicalize chains of tensor_cast operations (details)
  46. [compiler-rt] [scudo] Fix typo in function attribute (details)
  47. [ARM] Sink splats to MVE intrinsics (details)
  48. [amdgpu] Lower SGPR-to-VGPR copy in the final phase of ISel. (details)
  49. [libc++] Remove some workarounds for missing variadic templates (details)
  50. [Coroutine] Fix a bug where Coroutine incorrectly spills phi and invoke defs before CoroBegin (details)
  51. [OpenMP 5.0] Fix user-defined mapper privatization in tasks (details)
  52. [DFSan] Add bcmp wrapper. (details)
  53. Precommit test updates (details)
  54. [AArch64] Match pairwise add/fadd pattern (details)
  55. [CUDA][HIP] Defer overloading resolution diagnostics for host device functions (details)
  56. [ARM] Add more MVE postinc distribution tests. NFC (details)
  57. [mlir][openacc] Change operand type from index to AnyInteger in parallel op (details)
  58. [flang][openacc] Lower clauses on loop construct to OpenACC dialect (details)
  59. [Test] Add tests showing that IndVars cannot prove (X + 1 > X) (details)
  60. Revert "[DFSan] Add bcmp wrapper." (details)
  61. ModuloSchedule.cpp - remove unnecessary includes. NFCI. (details)
  62. Fix build failure in clangd (details)
  63. [mlir][Vector] Add a folder for vector.broadcast (details)
  64. [AArch64][GlobalISel] Fix bug in fewVectorElts action while legalizing oversize G_FPTRUNC vectors. (details)
  65. [ARM] Expand distributing increments to also handle existing pre/post inc instructions. (details)
  66. [InstSimplify] add tests for FP constant miscompile; NFC (PR43907) (details)
  67. [amdgpu] Compilation fix for Release (details)
  68. [SyntaxTree][Synthesis] Fix allocation in `createTree` for more general use (details)
  69. [DFSan] Add bcmp wrapper. (details)
  70. [Sema] Introduce BuiltinAttr, per-declaration builtin-ness (details)
Commit d49707cf4b288e8d3cad00a78cfa45ec4c376496 by jay.foad
[AMDGPU] Generate test checks for splitkit-copy-bundle.mir

This is a pre-commit for D87757 "[SplitKit] Only copy live lanes".
The file was modifiedllvm/test/CodeGen/AMDGPU/splitkit-copy-bundle.mir
Commit 6f6d389da5c37e5e9a900902f03dc649d57919b7 by jay.foad
[SplitKit] Only copy live lanes

When splitting a live interval with subranges, only insert copies for
the lanes that are live at the point of the split. This avoids some
unnecessary copies and fixes a problem where copying dead lanes was
generating MIR that failed verification. The test case for this is
test/CodeGen/AMDGPU/splitkit-copy-live-lanes.mir.

Without this fix, some earlier live range splitting would create %430:

%430 [256r,848r:0)[848r,2584r:1)  0@256r 1@848r L0000000000000003 [848r,2584r:0)  0@848r L0000000000000030 [256r,2584r:0)  0@256r weight:1.480938e-03
...
256B     undef %430.sub2:vreg_128 = V_LSHRREV_B32_e32 16, %20.sub1:vreg_128, implicit $exec
...
848B     %430.sub0:vreg_128 = V_AND_B32_e32 %92:sreg_32, %20.sub1:vreg_128, implicit $exec
...
2584B    %431:vreg_128 = COPY %430:vreg_128

Then RAGreedy::tryLocalSplit would split %430 into %432 and %433 just
before 848B giving:

%432 [256r,844r:0)  0@256r L0000000000000030 [256r,844r:0)  0@256r weight:3.066802e-03
%433 [844r,848r:0)[848r,2584r:1)  0@844r 1@848r L0000000000000030 [844r,2584r:0)  0@844r L0000000000000003 [844r,844d:0)[848r,2584r:1)  0@844r 1@848r weight:2.831776e-03
...
256B     undef %432.sub2:vreg_128 = V_LSHRREV_B32_e32 16, %20.sub1:vreg_128, implicit $exec
...
844B     undef %433.sub0:vreg_128 = COPY %432.sub0:vreg_128 {
           internal %433.sub2:vreg_128 = COPY %432.sub2:vreg_128
848B     }
  %433.sub0:vreg_128 = V_AND_B32_e32 %92:sreg_32, %20.sub1:vreg_128, implicit $exec
...
2584B    %431:vreg_128 = COPY %433:vreg_128

Note that the copy from %432 to %433 at 844B is a curious
bundle-without-a-BUNDLE-instruction that SplitKit creates deliberately,
and it includes a copy of .sub0 which is not live at this point, and
that causes it to fail verification:

*** Bad machine code: No live subrange at use ***
- function:    zextload_global_v64i16_to_v64i64
- basic block: %bb.0  (0x7faed48) [0B;2848B)
- instruction: 844B    undef %433.sub0:vreg_128 = COPY %432.sub0:vreg_128
- operand 1:   %432.sub0:vreg_128
- interval:    %432 [256r,844r:0)  0@256r L0000000000000030 [256r,844r:0)  0@256r weight:3.066802e-03
- at:          844B

Using real bundles with a BUNDLE instruction might also fix this
problem, but the current fix is less invasive and also avoids some
unnecessary copies.

https://bugs.llvm.org/show_bug.cgi?id=47492

Differential Revision: https://reviews.llvm.org/D87757
The file was modifiedllvm/test/CodeGen/AMDGPU/splitkit-copy-bundle.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/subreg-split-live-in-error.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
The file was modifiedllvm/lib/CodeGen/SplitKit.cpp
The file was addedllvm/test/CodeGen/AMDGPU/splitkit-copy-live-lanes.mir
Commit aadf55d1cea24a4e5384ab8546c3d794cb1ec724 by lebedev.ri
[NFC] EliminateDuplicatePHINodes(): small-size optimization: if there are <= 32 PHI's, O(n^2) algo is faster (geomean -0.08%)

This is functionally equivalent to the old implementation.

As per https://llvm-compile-time-tracker.com/compare.php?from=5f4e9bf6416e45eba483a4e5e263749989fdb3b3&to=4739e6e4eb54d3736e6457249c0919b30f6c855a&stat=instructions
this is a clear geomean compile-time regression-free win with overall geomean of `-0.08%`

32 PHI's appears to be the sweet spot; both the 16 and 64 performed worse:
https://llvm-compile-time-tracker.com/compare.php?from=5f4e9bf6416e45eba483a4e5e263749989fdb3b3&to=c4efe1fbbfdf0305ac26cd19eacb0c7774cdf60e&stat=instructions
https://llvm-compile-time-tracker.com/compare.php?from=5f4e9bf6416e45eba483a4e5e263749989fdb3b3&to=e4989d1c67010d3339d1a40ff5286a31f10cfe82&stat=instructions

If we have more PHI's than that, we fall-back to the original DenseSet-based implementation,
so the not-so-fast cases will still be handled.

However compile-time isn't the main motivation here.
I can name at least 3 limitations of this CSE:
1. Assumes that all PHI nodes have incoming basic blocks in the same order (can be fixed while keeping the DenseMap)
2. Does not special-handle `undef` incoming values (i don't see how we can do this with hashing)
3. Does not special-handle backedge incoming values (maybe can be fixed by hashing backedge as some magical value)

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D87408
The file was modifiedllvm/lib/Transforms/Utils/Local.cpp
Commit b03c2b8395ba94fb53f1e73a6473faedf628bbd9 by douglas.yung
Revert "Re-land: Add new hidden option -print-changed which only reports changes to IR"

The test added in this commit is failing on Windows bots:

http://lab.llvm.org:8011/builders/llvm-clang-win-x-armv7l/builds/1269

This reverts commit f9e6d1edc0dad9afb26e773aa125ed62c58f7080 and follow-up commit 6859d95ea2d0f3fe0de2923a3f642170e66a1a14.
The file was modifiedllvm/lib/Passes/StandardInstrumentations.cpp
The file was modifiedllvm/lib/IR/LegacyPassManager.cpp
The file was removedllvm/test/Other/change-printer.ll
The file was modifiedllvm/include/llvm/Passes/StandardInstrumentations.h
Commit a9cbe5cf30e386a4f44981f5bf9e1862ad36574d by ro
[X86] Fix stack alignment on 32-bit Solaris/x86

On Solaris/x86, several hundred 32-bit tests `FAIL`, all in the same way:

  env ASAN_OPTIONS=halt_on_error=false ./halt_on_error_suppress_equal_pcs.cpp.tmp
  Segmentation Fault (core dumped)

They segfault during startup:

  Thread 2 received signal SIGSEGV, Segmentation fault.
  [Switching to Thread 1 (LWP 1)]
  0x080f21f0 in __sanitizer::internal_mmap(void*, unsigned long, int, int, int, unsigned long long) () at /vol/llvm/src/llvm-project/dist/compiler-rt/lib/sanitizer_common/sanitizer_solaris.cpp:65
  65                              int prot, int flags, int fd, OFF_T offset) {
  1: x/i $pc
  => 0x80f21f0 <_ZN11__sanitizer13internal_mmapEPvmiiiy+16>: movaps 0x30(%esp),%xmm0
  (gdb) p/x $esp
  $3 = 0xfeffd488

The problem is that `movaps` expects 16-byte alignment, while 32-bit Solaris/x86
only guarantees 4-byte alignment following the i386 psABI.

This patch updates `X86Subtarget::initSubtargetFeatures` accordingly,
handles Solaris/x86 in the corresponding testcase, and allows for some
variation in address alignment in
`compiler-rt/test/ubsan/TestCases/TypeCheck/vptr.cpp`.

Tested on `amd64-pc-solaris2.11` and `x86_64-pc-linux-gnu`.

Differential Revision: https://reviews.llvm.org/D87615
The file was modifiedcompiler-rt/test/ubsan/TestCases/TypeCheck/vptr.cpp
The file was modifiedllvm/lib/Target/X86/X86Subtarget.cpp
The file was modifiedllvm/test/CodeGen/X86/stack-align2.ll
Commit c687af0c30b4dbdc9f614d5e061c888238e0f9c5 by david.spickett
[lldb] Don't send invalid region addresses to lldb server

Previously when <addr> in "memory region <addr>" didn't
parse correctly, we'd print an error then also ask lldb-server
for a region containing LLDB_INVALID_ADDRESS.

(lldb) memory region not_an_address
error: invalid address argument "not_an_address"...
error: Server returned invalid range

Only send the command to lldb-server if the address
parsed correctly.

(lldb) memory region not_an_address
error: invalid address argument "not_an_address"...

Reviewed By: labath

Differential Revision: https://reviews.llvm.org/D87694
The file was modifiedlldb/test/API/functionalities/memory-region/TestMemoryRegion.py
The file was modifiedlldb/source/Commands/CommandObjectMemory.cpp
Commit 9218f9283802b2d1ff33c490761fdb925b1e56d9 by cullen.rhodes
[clang][aarch64] ACLE: Support implicit casts between GNU and SVE vectors

This patch adds support for implicit casting between GNU vectors and SVE
vectors when `__ARM_FEATURE_SVE_BITS==N`, as defined by the Arm C
Language Extensions (ACLE, version 00bet5, section 3.7.3.3) for SVE [1].

This behavior makes it possible to use GNU vectors with ACLE functions
that operate on VLAT. For example:

  typedef int8_t vec __attribute__((vector_size(32)));
  vec f(vec x) { return svasrd_x(svptrue_b8(), x, 1); }

Tests are also added for implicit casting between GNU and fixed-length
SVE vectors created by the 'arm_sve_vector_bits' attribute. This
behavior makes it possible to use VLST with existing interfaces that
operate on GNUT. For example:

  typedef int8_t vec1 __attribute__((vector_size(32)));
  void f(vec1);
  #if __ARM_FEATURE_SVE_BITS==256 && __ARM_FEATURE_SVE_VECTOR_OPERATORS
  typedef svint8_t vec2 __attribute__((arm_sve_vector_bits(256)));
  void g(vec2 x) { f(x); } // OK
  #endif

The `__ARM_FEATURE_SVE_VECTOR_OPERATORS` feature macro indicates
interoperability with the GNU vector extension. This is the first patch
providing support for this feature, which once complete will be enabled
by the `-msve-vector-bits` flag, as the `__ARM_FEATURE_SVE_BITS` feature
currently is.

[1] https://developer.arm.com/documentation/100987/latest

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D87607
The file was modifiedclang/test/SemaCXX/attr-arm-sve-vector-bits.cpp
The file was modifiedclang/test/CodeGen/attr-arm-sve-vector-bits-cast.c
The file was modifiedclang/lib/AST/ASTContext.cpp
The file was modifiedclang/test/Sema/attr-arm-sve-vector-bits.c
Commit 347d59b16c71194d7a9372dd69d3e41ebeca3113 by limo
[mlir][Linalg] Convolution tiling added to ConvOp vectorization pass

ConvOp vectorization supports now only convolutions of static shapes with dimensions
of size either 3(vectorized) or 1(not) as underlying vectors have to be of static
shape as well. In this commit we add support for convolutions of any size as well as
dynamic shapes by leveraging existing matmul infrastructure for tiling of both input
and kernel to sizes accepted by the previous version of ConvOp vectorization.
In the future this pass can be extended to take "tiling mask" as a user input which
will enable vectorization of user specified dimensions.

Differential Revision: https://reviews.llvm.org/D87676
The file was modifiedmlir/integration_test/Dialect/Linalg/CPU/test-conv-3d-ncdhw-call.mlir
The file was modifiedmlir/integration_test/Dialect/Linalg/CPU/test-conv-1d-call.mlir
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp
The file was modifiedmlir/integration_test/Dialect/Linalg/CPU/test-conv-3d-call.mlir
The file was modifiedmlir/integration_test/Dialect/Linalg/CPU/test-conv-2d-call.mlir
The file was modifiedmlir/integration_test/Dialect/Linalg/CPU/test-conv-2d-nhwc-call.mlir
The file was modifiedmlir/test/Conversion/LinalgToVector/linalg-to-vector.mlir
The file was modifiedmlir/integration_test/Dialect/Linalg/CPU/test-conv-3d-ndhwc-call.mlir
The file was modifiedmlir/integration_test/Dialect/Linalg/CPU/test-conv-1d-ncw-call.mlir
The file was modifiedmlir/integration_test/Dialect/Linalg/CPU/test-conv-1d-nwc-call.mlir
The file was modifiedmlir/test/lib/Transforms/TestConvVectorization.cpp
The file was modifiedmlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h
The file was modifiedmlir/integration_test/Dialect/Linalg/CPU/test-conv-2d-nchw-call.mlir
Commit 4ae1bb193a596d5dab8e4e6acfcc081972b166a3 by llvm-dev
[AsmPrinter] Remove orphan DwarfUnit::shareAcrossDWOCUs declaration. NFCI.

Method implementation no longer exists.
The file was modifiedllvm/lib/CodeGen/AsmPrinter/DwarfUnit.h
Commit 8adf92e2d11ad23c946ae5bc10fc17505389e956 by llvm-dev
[AMDGPU] Remove orphan SITargetLowering::LowerINT_TO_FP declaration. NFCI.

Method implementation no longer exists.
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.h
Commit 550b1a6fd46f59134b2629ce23ca6a7874b45585 by llvm-dev
[AsmPrinter] DwarfDebug - use DebugLoc const references where possible. NFC.

Avoid unnecessary copies.
The file was modifiedllvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
Commit f108e71437c47cc5172af4a7f704bb3f69d392f2 by vincentzhaorz
[MLIR] Turns swapId into a FlatAffineConstraints member func

`swapId` used to be a static function in `AffineStructures.cpp`. This diff makes it accessible from the external world by turning it into a member function of `FlatAffineConstraints`. This will be very helpful for other projects that need to manipulate the content of `FlatAffineConstraints`.

Differential Revision: https://reviews.llvm.org/D87766
The file was modifiedmlir/include/mlir/Analysis/AffineStructures.h
The file was modifiedmlir/lib/Analysis/AffineStructures.cpp
Commit 504697e6f40ecad3da44aa43568b869780644353 by thakis
[gn build] (manually) port c9af34027bc
The file was modifiedllvm/utils/gn/secondary/compiler-rt/lib/builtins/BUILD.gn
Commit 68cfb02668550e3398c8ee8915732daf132f2652 by zinenko
[mlir] turn clang-format back on in C API test

C API test uses FileCheck comments inside C code and needs to
temporarily switch off clang-format to prevent it from messing with
FileCheck directives. A recently landed commit forgot to turn it back on
after a block of FileCheck comments. Fix that.
The file was modifiedmlir/test/CAPI/ir.c
Commit a615226743d0e986593961418efec76aedfa32b1 by david.green
[ARM] Extra fp16 bitcast tests. NFC
The file was modifiedllvm/test/CodeGen/ARM/fp16-bitcast.ll
Commit 71f237506b8fc06753eb733422d2fad20f622e2d by llvm-dev
DwarfFile.h - remove unnecessary includes. NFCI.

Use forward declarations where possible, move includes down to DwarfFile.cpp and avoid duplicate includes.
The file was modifiedllvm/lib/CodeGen/AsmPrinter/DwarfFile.h
The file was modifiedllvm/lib/CodeGen/AsmPrinter/DwarfFile.cpp
Commit 572e542c5e5fe2727502ab775a6b8c3d238c01b5 by llvm-dev
DwarfStringPool.cpp - remove unnecessary StringRef include. NFCI.

Already included in DwarfStringPool.h
The file was modifiedllvm/lib/CodeGen/AsmPrinter/DwarfStringPool.cpp
Commit fece1489d10bb189fe46bd08385ff6b8954dc39c by david.green
[ARM] Additional tests for qr intrinsics in loops. NFC
The file was addedllvm/test/CodeGen/Thumb2/mve-qrintr.ll
Commit c65627a1fe3be7521fc232d633bb6df577f55269 by david.spickett
Revert "[lldb] Don't send invalid region addresses to lldb server"

This reverts commit c687af0c30b4dbdc9f614d5e061c888238e0f9c5
due to a test failure on Windows.
The file was modifiedlldb/test/API/functionalities/memory-region/TestMemoryRegion.py
The file was modifiedlldb/source/Commands/CommandObjectMemory.cpp
Commit 97a476eb56726ef09bdd9c7f8c46d7e1c456d46b by sam.parker
[NFC][ARM] Tail fold test changes

Run update script on one test and add another.
The file was modifiedllvm/test/Transforms/LoopVectorize/ARM/tail-folding-not-allowed.ll
The file was addedllvm/test/Transforms/LoopVectorize/ARM/tail-fold-multiple-icmps.ll
Commit ed53ff4cde331e0ffeb492dca6281aaeea2cd8cf by llvm-dev
SymbolizableObjectFile.h - remove unnecessary includes. NFCI.

Use forward declarations where possible, move includes down to SymbolizableObjectFile.cpp and avoid duplicate includes.
The file was modifiedllvm/lib/DebugInfo/Symbolize/SymbolizableObjectFile.h
The file was modifiedllvm/lib/DebugInfo/Symbolize/SymbolizableObjectFile.cpp
Commit abe0d8551da52ea1d0d8ad5f9ad71d22a7cd9928 by llvm-dev
MetadataLoader.cpp - remove unnecessary StringRef include. NFCI.

Already included in MetadataLoader.h
The file was modifiedllvm/lib/Bitcode/Reader/MetadataLoader.cpp
Commit 40e771c1c0d33c687230111271060c2ba761269f by mydeveloperday
[clang-format][regression][PR47461] ifdef causes catch to be seen as a function

https://bugs.llvm.org/show_bug.cgi?id=47461

The following change {D80940} caused a regression in code which ifdef's around the try and catch block cause incorrect brace placement around the catch

```
  try
  {
  }
  catch (...) {
    // This is not a small function
    bar = 1;
  }
}
```

The brace after the catch will be placed on a newline

Reviewed By: curdeius

Differential Revision: https://reviews.llvm.org/D87291
The file was modifiedclang/lib/Format/FormatTokenLexer.cpp
The file was modifiedclang/unittests/Format/FormatTest.cpp
Commit bb037c2a7625d9d13a86b18d9b8b0c75eb8c91cb by mikael.holmen
[ConstraintSystem] Remove local variable that is set but not read [NFC]

gcc 7.4 warns about it.
The file was modifiedllvm/lib/Analysis/ConstraintSystem.cpp
Commit aa896a0b3a9d93df818fbe9b68644ad90bcda831 by llvm-dev
Remove unnecessary forward declarations. NFCI.

All of these forward declarations are fully defined in headers that are directly included.
The file was modifiedllvm/include/llvm/MC/MCELFObjectWriter.h
The file was modifiedllvm/include/llvm/IR/LegacyPassManagers.h
The file was modifiedllvm/include/llvm/Transforms/Utils/LoopVersioning.h
The file was modifiedllvm/include/llvm/DebugInfo/PDB/PDBSymbol.h
The file was modifiedllvm/include/llvm/ExecutionEngine/Orc/CompileUtils.h
The file was modifiedllvm/include/llvm/ProfileData/SampleProf.h
The file was modifiedllvm/include/llvm/MC/MCParser/MCTargetAsmParser.h
The file was modifiedllvm/include/llvm/Transforms/Utils/LoopUtils.h
The file was modifiedllvm/include/llvm/ExecutionEngine/Orc/GlobalMappingLayer.h
Commit 788c7d2ec11dfc868a5b03478c922dc9699c6d47 by jrtc27
[clang][docs] Fix documentation of -O

D79916 changed the behaviour from -O2 to -O1 but the documentation was
not updated to reflect this.
The file was modifiedclang/docs/CommandGuide/clang.rst
Commit 03783f19dc78fc45fd987f892c314578b5e52d78 by spatel
[SLP] sort candidates to increase chance of optimal compare reduction

This is one (small) part of improving PR41312:
https://llvm.org/PR41312

As shown there and in the smaller tests here, if we have some member of the
reduction values that does not match the others, we want to push it to the
end (bring the matching members forward and together).

In the regression tests, we have 5 candidates for the 4 slots of the reduction.
If the one "wrong" compare is grouped with the others, it prevents forming the
ideal v4i1 compare reduction.

Differential Revision: https://reviews.llvm.org/D87772
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/compare-reduce.ll
Commit 0dca1ac617d802c0806f57f67eb830c4f5f3fffb by grimar
[llvm-readelf/obj][test] - Document what we print in various places for unnamed section symbols.

We have an issue with `ELFDumper<ELFT>::getSymbolSectionName`:
1) It is used deeply for both LLVM/GNU styles and might return LLVM-style only
   values to describe symbols: "Undefined", "Processor Specific", "Absolute", etc.

2) `getSymbolSectionName` is used by `getFullSymbolName` and these special values
   might appear in instead of symbol names in many places.
   This occurs for unnamed section symbols.

It was not noticed because for most cases I've found it is unexpected to have an
unnamed section symbol. This patch documents the existent behavior, adds tests and FIXMEs.

Differential revision: https://reviews.llvm.org/D87763
The file was modifiedllvm/test/tools/llvm-readobj/ELF/dyn-symbols.test
The file was modifiedllvm/test/tools/llvm-readobj/ELF/symbol-shndx.test
The file was modifiedllvm/test/tools/llvm-readobj/ELF/hash-symbols.test
The file was modifiedllvm/test/tools/llvm-readobj/ELF/mips-plt.test
The file was modifiedllvm/test/tools/llvm-readobj/ELF/mips-got.test
Commit 279943edf87887403fce72c505f9760764e416f0 by grimar
[obj2yaml] - Don't emit EM_NONE.

When ELF header's `e_machine == 0`, we emit:

```
Machine: EM_NONE
```

We can avoid doing this, because yaml2obj sets the
`e_machine` field to `EM_NONE` by default.

Differential revision: https://reviews.llvm.org/D87829
The file was modifiedllvm/test/tools/obj2yaml/ELF/versym-section.yaml
The file was modifiedllvm/test/tools/obj2yaml/ELF/null-section.yaml
The file was modifiedllvm/test/tools/obj2yaml/ELF/gnu-unique-symbols.yaml
The file was modifiedllvm/test/tools/obj2yaml/ELF/emachine.yaml
The file was modifiedllvm/test/tools/obj2yaml/ELF/implicit-sections-order.yaml
The file was modifiedllvm/test/tools/obj2yaml/ELF/invalid-section-name.yaml
The file was modifiedllvm/test/tools/obj2yaml/ELF/duplicate-symbol-and-section-names.yaml
The file was modifiedllvm/test/tools/obj2yaml/ELF/no-symtab.yaml
The file was modifiedllvm/test/tools/obj2yaml/ELF/stack-sizes.yaml
The file was modifiedllvm/test/tools/obj2yaml/ELF/sht-symtab-shndx.yaml
The file was modifiedllvm/tools/obj2yaml/elf2yaml.cpp
The file was modifiedllvm/test/tools/obj2yaml/ELF/call-graph-profile-section.yaml
The file was modifiedllvm/test/tools/obj2yaml/ELF/symbol-visibility.yaml
Commit f7185b271f5b3010c82a56417b437f2a44a79230 by kerry.mclaughlin
[SVE][CodeGen] Lower floating point -> integer conversions

This patch adds new ISD nodes, FCVTZS_MERGE_PASSTHRU &
FCVTZU_MERGE_PASSTHRU, which are used to lower scalable vector
FP_TO_SINT/FP_TO_UINT operations and the following intrinsics:
- llvm.aarch64.sve.fcvtzu
- llvm.aarch64.sve.fcvtzs

Reviewed By: efriedma, paulwalker-arm

Differential Revision: https://reviews.llvm.org/D87232
The file was modifiedllvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
The file was modifiedllvm/lib/Target/AArch64/SVEInstrFormats.td
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.h
The file was addedllvm/test/CodeGen/AArch64/sve-fcvt.ll
The file was addedllvm/test/CodeGen/AArch64/sve-split-fcvt.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
Commit 9dc1e53787abbf4f2624c73272bf00e23fdffba0 by flo
[MemorySSA] Add another loop clobber test case.
The file was modifiedllvm/test/Analysis/MemorySSA/phi-translation.ll
Commit deb8f8bcf31540c657716ea5242183b0792702a1 by yvan.roux
[ARM][MachineOutliner] Add missing testcase for calls.
The file was addedllvm/test/CodeGen/ARM/machine-outliner-calls.mir
Commit f026812110878484d003f18660492e9321ef2df1 by llvm-dev
InstCombiner.h - remove unnecessary KnownBits.h include. NFCI.

Move the include down to cpp files with an implicit dependency.
The file was modifiedllvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
The file was modifiedllvm/lib/Target/X86/X86InstCombineIntrinsic.cpp
The file was modifiedllvm/include/llvm/Transforms/InstCombine/InstCombiner.h
The file was modifiedllvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
Commit e4a198eeee3ca96ff324d5b786e44c4915334054 by zhuoryin
[AMDGPU] Bump to ROCm 3.7 dependency hip_hcc->amdhip64

Differential Revision: https://reviews.llvm.org/D87773
The file was modifiedmlir/tools/mlir-rocm-runner/CMakeLists.txt
Commit 67ae46c820fa680e7f5828b4d8b94a562f51c9bf by llvm-dev
SafeStackLayout.cpp - remove unnecessary StackLifetime.h include. NFCI.

Already included in SafeStackLayout.h
The file was modifiedllvm/lib/CodeGen/SafeStackLayout.cpp
Commit 69516ddd028e8314f575a90bfca1724818fb5ca6 by n54
[compiler-rt] Avoid pulling libatomic to sanitizer tests

Avoid fallbacking to software emulated compiler atomics, that are usually
provided by libatomic, which is not always present.

This fixes the test on NetBSD, which does not provide libatomic in base.

Reviewed By: vitalybuka

Differential Revision: https://reviews.llvm.org/D87568
The file was modifiedcompiler-rt/lib/sanitizer_common/tests/sanitizer_atomic_test.cpp
Commit d566771779cd408bbe4985ea56e9b3c2ba247ed3 by llvm-dev
ValueList.cpp - remove unnecessary includes. NFCI.

Already included in ValueList.h
The file was modifiedllvm/lib/Bitcode/Reader/ValueList.cpp
Commit 46e59062a0e25be6e29d3fb342402f69b0e470b1 by llvm-dev
DwarfExpression.cpp - remove unnecessary includes. NFCI.

Already included in DwarfExpression.h
The file was modifiedllvm/lib/CodeGen/AsmPrinter/DwarfExpression.cpp
Commit 85ba2f16633638e55ebc8e84bfbd0aaaa2f72b7a by llvm-dev
LiveDebugVariables.cpp - remove unnecessary Compiler.h include. NFCI.

Already included in LiveDebugVariables.h
The file was modifiedllvm/lib/CodeGen/LiveDebugVariables.cpp
Commit 85e578f53ad1ba21771470dc9516068a259d29cf by n54
[compiler-rt] Replace INLINE with inline

This fixes the clash with BSD headers.

Reviewed By: vitalybuka

Differential Revision: https://reviews.llvm.org/D87562
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_mac.h
The file was modifiedcompiler-rt/lib/asan/asan_malloc_linux.cpp
The file was modifiedcompiler-rt/lib/scudo/scudo_crc32.h
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_atomic_clang_x86.h
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_atomic_msvc.h
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_common.h
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_allocator.h
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_interceptors.h
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_allocator_secondary.h
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_atomic_clang_other.h
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_internal_defs.h
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_linux_libcdep.cpp
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_rtl.h
The file was modifiedcompiler-rt/lib/asan/asan_malloc_local.h
The file was modifiedcompiler-rt/lib/scudo/scudo_utils.h
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_linux.h
The file was modifiedcompiler-rt/lib/scudo/scudo_utils.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_symbolizer_report.cpp
The file was modifiedcompiler-rt/lib/msan/tests/msan_test.cpp
The file was modifiedcompiler-rt/lib/scudo/scudo_tsd.h
The file was modifiedcompiler-rt/lib/asan/asan_report.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_atomic_clang.h
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_atomic_clang_mips.h
The file was modifiedcompiler-rt/lib/scudo/scudo_allocator.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_platform_limits_freebsd.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_atomic.h
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_allocator_checks.h
Commit 9339f68f21facc34fb0901045d571c818e1fa84a by n54
[compiler-rt] [tsan] [netbsd] Catch unsupported LONG_JMP_SP_ENV_SLOT

Error out during build for unsupported CPU.

Reviewed By: vitalybuka

Differential Revision: https://reviews.llvm.org/D87602
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_platform_linux.cpp
Commit 0efbb70b719e990fe153373eda5a604344ae36bb by Alexander Timofeev
[AMDGPU] should expand ROTL i16 to shifts.

Instruction combining pass turns library rotl implementation to llvm.fshl.i16.
In the selection dag the intrinsic is turned to ISD::ROTL node that cannot be selected.
Need to expand it to shifts again.

Reviewed By: rampitec, arsenm

Differential Revision: https://reviews.llvm.org/D87618
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/rotl.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/rotr.ll
Commit 72c5feeed8d8d570e1c971ef069483491463a003 by n54
[compiler-rt] [netbsd] Include <sys/dkbad.h>

Fixes build on NetBSD/sparc64.
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_platform_limits_netbsd.cpp
Commit e7de267910e935ab885dae22b5191bfb118ca5f9 by n54
[compiler-rt] [hwasan] Replace INLINE with inline

Fixes the build after landing D87562.
The file was modifiedcompiler-rt/lib/hwasan/hwasan_malloc_bisect.h
Commit 5e0ded268929b87ddf2c5e077c9185554342f602 by herhut
[mlir][Standard] Canonicalize chains of tensor_cast operations

Adds a pattern that replaces a chain of two tensor_cast operations by a single tensor_cast operation if doing so will not remove constraints on the shapes.
The file was modifiedmlir/test/Transforms/canonicalize.mlir
The file was modifiedmlir/lib/Dialect/StandardOps/IR/Ops.cpp
The file was modifiedmlir/include/mlir/Dialect/StandardOps/IR/Ops.td
Commit 7b2dd58eb09d3ead649bdd0a67f69d8776a636ff by n54
[compiler-rt] [scudo] Fix typo in function attribute

Fixes the build after landing https://reviews.llvm.org/D87562
The file was modifiedcompiler-rt/lib/scudo/scudo_allocator.cpp
Commit 34b27b9441d27ef886ea22b3bb75b357a5ec707b by david.green
[ARM] Sink splats to MVE intrinsics

The predicated MVE intrinsics are generated as, for example,
llvm.arm.mve.add.predicated(x, splat(y). p). We need to sink the splat
value back into the loop, like we do for other instructions, so we can
re-select qr variants.

Differential Revision: https://reviews.llvm.org/D87693
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-operand.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-qrintr.ll
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
The file was modifiedllvm/test/CodeGen/Thumb2/mve-postinc-lsr.ll
Commit c3492a1aa1b98c8d81b0969d52cea7681f0624c2 by michael.hliao
[amdgpu] Lower SGPR-to-VGPR copy in the final phase of ISel.

- Need to lower COPY from SGPR to VGPR to a real instruction as the
  standard COPY is used where the source and destination are from the
  same register bank so that we potentially coalesc them together and
  save one COPY. Considering that, backend optimizations, such as CSE,
  won't handle them. However, the copy from SGPR to VGPR always needs
  materializing to a native instruction, it should be lowered into a
  real one before other backend optimizations.

Differential Revision: https://reviews.llvm.org/D87556
The file was modifiedllvm/lib/Target/AMDGPU/SIFoldOperands.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/wqm.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/fabs.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
The file was addedllvm/test/CodeGen/AMDGPU/sgpr-copy-cse.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/fneg-fabs.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/waitcnt-vscnt.ll
Commit a3c28ccd49391931acd8b3b27dc98d7c606051e0 by Louis Dionne
[libc++] Remove some workarounds for missing variadic templates

We don't support GCC in C++03 mode, and Clang provides variadic templates
even in C++03 mode. So there's effectively no supported compiler that
doesn't support variadic templates.

This effectively gets rid of all uses of _LIBCPP_HAS_NO_VARIADICS, but
some workarounds for the lack of variadics remain.
The file was modifiedlibcxx/include/__config
The file was modifiedlibcxx/include/type_traits
The file was removedlibcxx/test/std/utilities/meta/meta.unary/meta.unary.cat/member_function_pointer_no_variadics.pass.cpp
The file was modifiedlibcxx/include/memory
The file was modifiedlibcxx/include/future
Commit 5b533d6cdeed21369dee4572b5485b1fd5d5dcf5 by xun
[Coroutine] Fix a bug where Coroutine incorrectly spills phi and invoke defs before CoroBegin

When a spill definition is before CoroBegin, we cannot spill it to the frame immediately after the definition. We have to spill it after the frame is ready.
The current implementation handles it properly for any other kinds of instructions except for PhINode and InvokeInst, which could also be defined before CoroBegin.
This patch fixes it by moving the CoroBegin dominance check earlier, so that it covers all cases.
Added a test.

Differential Revision: https://reviews.llvm.org/D87810
The file was addedllvm/test/Transforms/Coroutines/coro-spill-defs-before-corobegin.ll
The file was modifiedllvm/lib/Transforms/Coroutines/CoroFrame.cpp
Commit d5ce8233bfcfdeb66c715a1def8e0b34d236d48a by a.bataev
[OpenMP 5.0] Fix user-defined mapper privatization in tasks

This patch fixes the problem that user-defined mapper array is not correctly privatized inside a task. This problem causes openmp/libomptarget/test/offloading/target_depend_nowait.cpp fails.

Differential Revision: https://reviews.llvm.org/D84470
The file was modifiedclang/test/OpenMP/target_depend_codegen.cpp
The file was modifiedclang/lib/CodeGen/CGOpenMPRuntime.cpp
Commit 559f9198125392bfa8e7d462aa8e87fcf5030185 by mascasa
[DFSan] Add bcmp wrapper.

Reviewed By: vitalybuka

Differential Revision: https://reviews.llvm.org/D87801
The file was modifiedcompiler-rt/lib/dfsan/done_abilist.txt
The file was modifiedcompiler-rt/lib/dfsan/dfsan_custom.cpp
The file was modifiedcompiler-rt/test/dfsan/custom.cpp
Commit 3ee87a976d52a2379d007046f9a1ad4a07f440c0 by Sanne.Wouda
Precommit test updates
The file was addedllvm/test/CodeGen/AArch64/faddp-half.ll
The file was modifiedllvm/test/CodeGen/AArch64/vecreduce-fadd.ll
The file was addedllvm/test/CodeGen/AArch64/faddp.ll
Commit d5fd3d9b903ef6d96c6b3b82434dd0461faaba55 by Sanne.Wouda
[AArch64] Match pairwise add/fadd pattern

D75689 turns the faddp pattern into a shuffle with vector add.

Match this new pattern in target-specific DAG combine, rather than ISel,
because legalization (for v2f32) turns it into a bit of a mess.

- extended to cover f16, f32, f64 and i64
The file was modifiedllvm/test/CodeGen/AArch64/vecreduce-fadd.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.td
The file was modifiedllvm/test/CodeGen/AArch64/faddp.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/AArch64/faddp-half.ll
Commit 40df06cdafc010002fc9cfe1dda73d689b7d27a6 by Yaxun.Liu
[CUDA][HIP] Defer overloading resolution diagnostics for host device functions

In CUDA/HIP a function may become implicit host device function by
pragma or constexpr. A host device function is checked in both
host and device compilation. However it may be emitted only
on host or device side, therefore the diagnostics should be
deferred until it is known to be emitted.

Currently clang is only able to defer certain diagnostics. This causes
false alarms and limits the usefulness of host device functions.

This patch lets clang defer all overloading resolution diagnostics for host device functions.

An option -fgpu-defer-diag is added to control this behavior. By default
it is off.

It is NFC for other languages.

Differential Revision: https://reviews.llvm.org/D84364
The file was modifiedclang/lib/Sema/SemaTemplateInstantiate.cpp
The file was modifiedclang/test/TableGen/DiagnosticBase.inc
The file was modifiedclang/lib/Sema/SemaOverload.cpp
The file was modifiedclang/include/clang/Basic/Diagnostic.td
The file was modifiedclang/lib/Driver/ToolChains/HIP.cpp
The file was modifiedclang/lib/Sema/SemaStmt.cpp
The file was modifiedclang/include/clang/Basic/DiagnosticSerialization.h
The file was modifiedclang/include/clang/Basic/DiagnosticIDs.h
The file was modifiedclang/lib/Sema/SemaTemplateInstantiateDecl.cpp
The file was modifiedclang/include/clang/Basic/DiagnosticSema.h
The file was modifiedclang/lib/Sema/SemaStmtAsm.cpp
The file was modifiedclang/lib/Sema/SemaCUDA.cpp
The file was addedclang/test/TableGen/deferred-diag.td
The file was modifiedclang/include/clang/Driver/Options.td
The file was modifiedclang/include/clang/Basic/DiagnosticComment.h
The file was modifiedclang/include/clang/Basic/DiagnosticRefactoring.h
The file was modifiedclang/include/clang/Basic/DiagnosticLex.h
The file was modifiedclang/lib/Sema/SemaSYCL.cpp
The file was modifiedclang/lib/Sema/SemaType.cpp
The file was modifiedclang/lib/Sema/Sema.cpp
The file was modifiedclang/lib/Driver/ToolChains/Cuda.cpp
The file was modifiedclang/lib/Sema/AnalysisBasedWarnings.cpp
The file was modifiedclang/lib/Sema/SemaTemplateVariadic.cpp
The file was modifiedclang/lib/Sema/SemaAttr.cpp
The file was modifiedclang/include/clang/Basic/DiagnosticFrontend.h
The file was modifiedclang/include/clang/Basic/DiagnosticSemaKinds.td
The file was modifiedclang/lib/Sema/SemaOpenMP.cpp
The file was modifiedclang/utils/TableGen/ClangDiagnosticsEmitter.cpp
The file was modifiedclang/include/clang/Basic/DiagnosticDriver.h
The file was modifiedclang/include/clang/Basic/DiagnosticParse.h
The file was modifiedclang/lib/Basic/DiagnosticIDs.cpp
The file was modifiedclang/tools/diagtool/DiagnosticNames.cpp
The file was modifiedclang/include/clang/Basic/DiagnosticAST.h
The file was modifiedclang/include/clang/Basic/DiagnosticAnalysis.h
The file was addedclang/test/SemaCUDA/deferred-oeverload.cu
The file was modifiedclang/include/clang/Basic/DiagnosticCrossTU.h
The file was modifiedclang/include/clang/Sema/Sema.h
The file was modifiedclang/include/clang/Basic/LangOptions.def
The file was modifiedclang/lib/Frontend/CompilerInvocation.cpp
The file was modifiedclang/lib/Sema/SemaDecl.cpp
The file was modifiedclang/lib/Sema/SemaExprObjC.cpp
Commit 72a4a478fe12f3052d1f73c5e5b4a905c8dfcf1b by david.green
[ARM] Add more MVE postinc distribution tests. NFC
The file was modifiedllvm/test/CodeGen/Thumb2/mve-postinc-distribute.mir
Commit 6d3cabd90eedee07a6e6cbf2dfa952e23cef192c by clementval
[mlir][openacc] Change operand type from index to AnyInteger in parallel op

This patch change the type of operands async, wait, numGangs, numWorkers and vectorLength from index
to AnyInteger to fit with acc.loop and the OpenACC specification.

Reviewed By: ftynse

Differential Revision: https://reviews.llvm.org/D87712
The file was modifiedmlir/test/Dialect/OpenACC/ops.mlir
The file was modifiedmlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
The file was modifiedmlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
Commit f0e028f4b32393676b5d3eb36d6598ec5a390180 by clementval
[flang][openacc] Lower clauses on loop construct to OpenACC dialect

Lower OpenACCLoopConstruct and most of the clauses to the OpenACC acc.loop operation in MLIR.
This patch refelcts what can be upstream from PR flang-compiler/f18-llvm-project#419

Reviewed By: SouraVX

Differential Revision: https://reviews.llvm.org/D87389
The file was modifiedflang/include/flang/Optimizer/Dialect/FIRDialect.h
The file was modifiedflang/lib/Lower/OpenACC.cpp
Commit 7688027f166311164982bb15fe44041f31b6d45f by mkazantsev
[Test] Add tests showing that IndVars cannot prove (X + 1 > X)
The file was addedllvm/test/Transforms/IndVarSimplify/trivial-checks.ll
Commit df017fd906bba81af38749fe374ae2635fd51389 by mascasa
Revert "[DFSan] Add bcmp wrapper."

This reverts commit 559f9198125392bfa8e7d462aa8e87fcf5030185 due to bot
failure.
The file was modifiedcompiler-rt/lib/dfsan/dfsan_custom.cpp
The file was modifiedcompiler-rt/lib/dfsan/done_abilist.txt
The file was modifiedcompiler-rt/test/dfsan/custom.cpp
Commit 2a56a0ba086491e51c54026c6badae6496539487 by llvm-dev
ModuloSchedule.cpp - remove unnecessary includes. NFCI.

Already included in ModuloSchedule.h
The file was modifiedllvm/lib/CodeGen/ModuloSchedule.cpp
Commit 7f1f89ec8d9944559042bb6d3b1132eabe3409de by Yaxun.Liu
Fix build failure in clangd
The file was modifiedclang-tools-extra/clangd/Diagnostics.cpp
Commit f16abe5f84eee8db18d5eb5a21ab543146626ea6 by hanchung
[mlir][Vector] Add a folder for vector.broadcast

Fold the operation if the source is a scalar constant or splat constant.

Update transform-patterns-matmul-to-vector.mlir because the broadcast ops are folded in the conversion.

Reviewed By: aartbik

Differential Revision: https://reviews.llvm.org/D87703
The file was modifiedmlir/test/Dialect/Linalg/transform-patterns-matmul-to-vector.mlir
The file was modifiedmlir/test/Dialect/Vector/canonicalize.mlir
The file was modifiedmlir/include/mlir/Dialect/Vector/VectorOps.td
The file was modifiedmlir/lib/Dialect/Vector/VectorOps.cpp
Commit 79b21fc187643416dbd21db10abe46a91b4c3f09 by Amara Emerson
[AArch64][GlobalISel] Fix bug in fewVectorElts action while legalizing oversize G_FPTRUNC vectors.

For <8 x s32> = fptrunc <8 x s64> the fewerElementsVector action tries to break
down the source vector into the final source vectors of <2 x s64> using unmerge.
This fixes a crash due to using the wrong number of elements for the breakdown
type.

Also add some legalizer tests for explicitly G_FPTRUNC which we didn't have.

Differential Revision: https://reviews.llvm.org/D87814
The file was modifiedllvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
The file was modifiedllvm/test/CodeGen/AArch64/arm64-vcvt.ll
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/legalize-fptrunc.mir
Commit 7f7993e0daf459c308747f034e3fbd73889c7ab3 by david.green
[ARM] Expand distributing increments to also handle existing pre/post inc instructions.

This extends the distributing postinc code in load/store optimizer to
also handle the case where there is an existing pre/post inc instruction,
where subsequent instructions can be modified to use the adjusted
offset from the increment. This can save us having to keep the old
register live past the increment instruction.

Differential Revision: https://reviews.llvm.org/D83377
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vst2.ll
The file was modifiedllvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
The file was modifiedllvm/test/CodeGen/Thumb2/mve-postinc-distribute.mir
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vst3.ll
Commit c6ebe3fd002c1d3b903ab6e912ebd815fdb0e964 by spatel
[InstSimplify] add tests for FP constant miscompile; NFC (PR43907)
The file was modifiedllvm/test/Transforms/InstSimplify/ConstProp/cast.ll
Commit 7d593d0d6905b55ca1124fca5e4d1ebb17203138 by benny.kra
[amdgpu] Compilation fix for Release

Reviewed By: bkramer

Differential Revision: https://reviews.llvm.org/D87838
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
Commit 1e19165bd89db6671a80e0b25b32d5c7ae79455c by ecaldas
[SyntaxTree][Synthesis] Fix allocation in `createTree` for more general use

Prior to this change `createTree` could not create arbitrary syntax
trees. Now it dispatches to the constructor of the concrete syntax tree
according to the `NodeKind` passed as argument. This allows reuse inside
the Synthesis API.  # Please enter the commit message for your changes.
Lines starting

Differential Revision: https://reviews.llvm.org/D87820
The file was modifiedclang/include/clang/Tooling/Syntax/BuildTree.h
The file was modifiedclang/lib/Tooling/Syntax/Synthesis.cpp
Commit 50dd545b00ed72a9ed2031cb5eb9bf26dd5af0c0 by mascasa
[DFSan] Add bcmp wrapper.

Reviewed By: vitalybuka

Differential Revision: https://reviews.llvm.org/D87801
The file was modifiedcompiler-rt/lib/dfsan/done_abilist.txt
The file was modifiedcompiler-rt/lib/dfsan/dfsan_custom.cpp
The file was modifiedcompiler-rt/test/dfsan/custom.cpp
Commit e09107ab80dced55414fa458cf78e6cdfe90da6e by raul.tambre
[Sema] Introduce BuiltinAttr, per-declaration builtin-ness

Instead of relying on whether a certain identifier is a builtin, introduce BuiltinAttr to specify a declaration as having builtin semantics.

This fixes incompatible redeclarations of builtins, as reverting the identifier as being builtin due to one incompatible redeclaration would have broken rest of the builtin calls.
Mostly-compatible redeclarations of builtins also no longer have builtin semantics. They don't call the builtin nor inherit their attributes.
A long-standing FIXME regarding builtins inside a namespace enclosed in extern "C" not being recognized is also addressed.

Due to the more correct handling attributes for builtin functions are added in more places, resulting in more useful warnings.
Tests are updated to reflect that.

Intrinsics without an inline definition in intrin.h had `inline` and `static` removed as they had no effect and caused them to no longer be recognized as builtins otherwise.

A pthread_create() related test is XFAIL-ed, as it relied on it being recognized as a builtin based on its name.
The builtin declaration syntax is too restrictive and doesn't allow custom structs, function pointers, etc.
It seems to be the only case and fixing this would require reworking the current builtin syntax, so this seems acceptable.

Fixes PR45410.

Reviewed By: rsmith, yutsumi

Differential Revision: https://reviews.llvm.org/D77491
The file was modifiedclang/test/SemaCXX/cxx11-compat.cpp
The file was modifiedclang/include/clang/Basic/Attr.td
The file was modifiedclang/lib/AST/Decl.cpp
The file was modifiedclang/include/clang/Sema/Sema.h
The file was modifiedclang/lib/Sema/SemaExpr.cpp
The file was modifiedclang/lib/Headers/intrin.h
The file was modifiedclang/lib/Serialization/ASTWriter.cpp
The file was modifiedclang/lib/Sema/SemaLookup.cpp
The file was modifiedclang/test/Sema/implicit-builtin-decl.c
The file was modifiedclang/lib/Serialization/ASTReader.cpp
The file was modifiedclang/test/CodeGen/callback_pthread_create.c
The file was modifiedclang/test/AST/ast-dump-attr.cpp
The file was addedclang/test/CodeGen/builtin-redeclaration.c
The file was modifiedclang/include/clang/Basic/IdentifierTable.h
The file was modifiedclang/include/clang/Basic/Builtins.def
The file was modifiedclang/test/Sema/warn-fortify-source.c
The file was modifiedclang/test/SemaCXX/warn-unused-local-typedef.cpp
The file was modifiedclang/lib/Sema/SemaDecl.cpp
The file was modifiedclang/test/CodeGenCXX/builtins.cpp

Summary

  1. clang-x86-ninja-win10: removed DIA flag, added LIBZ flag (details)
Commit 3b3349e94a30eb9608e44f335ba74119311d714c by kuhnel
clang-x86-ninja-win10: removed DIA flag, added LIBZ flag
The file was modifiedbuildbot/osuosl/master/config/builders.py