FailedChanges

Changes from Git (git http://labmaster3.local/git/llvm-project.git)

Summary

  1. [lldb] [doc] Status: Linux: Update the paragraph (details)
  2. [X86] Rename matchShuffleAsRotate - matchShuffleAsByteRotate. NFCI. (details)
  3. [X86][SSE] Add more tests showing failure to lower shuffles as bit rotations (details)
  4. [X86][XOP] Add XOP target to vXi16/vXi8 shuffle tests (details)
  5. libclc: Move rsqrt implementation to a .cl file (details)
  6. libclc/r600: Use target specific builtins to implement rsqrt and native_rsqrt (details)
  7. [X86] Remove isel patterns that include a vselect/X86selects and a strict FP node. (details)
  8. [X86] Use MVT::i32 for the type of a MOV32r0 created in X86DAGToDAGISel::Select. (details)
  9. [X86] Add lowerShuffleAsBitRotate (PR44379) (details)
  10. [X86] Add flag result VT to a MOV32r0 created in X86DAGToDAGISel::Select (details)
  11. [X86] Use custom isel for (X86sbb_flag 0, 0) so we can use 32-bit SBB for i8/i16. (details)
  12. [X86] combineConcatVectorOps - combine VROTLI/VROTRI ops (details)
  13. AMDGPU: Fix SI_IF lowering when the save exec reg has terminator uses (details)
  14. AMDGPU: Remove dead kill handling (details)
  15. AMDGPU/GlobalISel: Look through casts when legalizing vector indexing (details)
  16. AMDGPU/GlobalISel: Don't mis-select vector index on a constant (details)
  17. GlobalISel: Fix narrowing of G_CTLZ/G_CTTZ (details)
  18. AMDGPU/GlobalISel: Split 64-bit G_CTPOP in RegBankSelect (details)
  19. GlobalISel: Fix narrowScalar for G_{CTLZ|CTTZ}_ZERO_UNDEF (details)
  20. [DebugInfo] Add a DWARFDataExtractor constructor that takes ArrayRef<uint8_t> (details)
  21. [RISCV] Fix incorrect FP base CFI offset for variable argument functions (details)
  22. [X86] Use MOVZX instead of MOVSX in f16_to_fp isel patterns. (details)
  23. [X86] Autogenerate complete checks. NFC (details)
  24. [clang][codegen] Fix another lifetime emission on alloca on non-default address space. (details)
  25. Fix `-Wparentheses` warning. NFC. (details)
  26. [X86] Make (insert_vector_elt (v8i16 zerovec), i16 %x, 0) generate the same code as (v8i16 (build_vector %x, 0, 0, 0, 0, 0, 0, 0)). (details)
  27. [Attributor][NFC] Use existing constant instead of magic one (details)
  28. [Attributor][Tests][NFC] Add more range tests (details)
  29. [X86] Autogenerate complete checks. NFC (details)
  30. [Attributor][FIX] Call right base method in AAValueConstantRangeFloating (details)
  31. [Attributor] Look through (some) casts in AAValueConstantRangeFloating (details)
  32. [Attributor] Allow SelectInst in AAValueConstantRangeFloating (details)
  33. [Attributor][FIX] Remove FIXME that seems outdated (details)
  34. [Attributor] Allow PHI nodes in AAValueConstantRangeFloating (details)
  35. [GlobalISel][CallLowering] Tighten constantexpr check for callee. (details)
  36. [llvm-dwarfdump][Stats] Fix the License header (details)
  37. [Attributor][Tests] Run the CGSCC versions on the range.ll test (details)
  38. [Attributor] Simple casts preserve no-alias property (details)
  39. [Attributor][FIX] Make check lines explicit (details)
  40. [AMDGPU] Add a16 feature to gfx10 (details)
  41. [lldb] Refactored TestCallOverriddenMethod.py to general virtual function test (details)
  42. [lldb] [doc] Change sample commands prefix from > to $ (details)
  43. [CSInfo] Use isCandidateForCallSiteEntry() when updating the CSInfo (details)
  44. [SytemZ] Disable vector ABI when using option -march=arch[8|9|10] (details)
  45. [LLDB] Fix GCC warnings about extra semicolons. NFC. (details)
Commit 9d223a0106d0bde18aa6e353ec338206b235e3f2 by jan.kratochvil
[lldb] [doc] Status: Linux: Update the paragraph
The file was modifiedlldb/docs/status/status.rst
Commit 29621b2534658426128ec30455db98c105964c51 by llvm-dev
[X86] Rename matchShuffleAsRotate - matchShuffleAsByteRotate. NFCI.

A matchShuffleAsBitRotate variant will be added soon and we need to make the difference more obvious.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit 22780731255020ce78cf3671a4af94c4a2e9ac03 by llvm-dev
[X86][SSE] Add more tests showing failure to lower shuffles as bit rotations
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-256-v32.ll
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-512-v32.ll
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-128-v16.ll
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-128-v8.ll
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-256-v16.ll
Commit 0ae119f83560c694d6b1f17e32dc7a6b8be16bc1 by llvm-dev
[X86][XOP] Add XOP target to vXi16/vXi8 shuffle tests

Helps with bit rotation test coverage for PR44379
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-256-v16.ll
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-128-v16.ll
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-256-v32.ll
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-128-v8.ll
Commit 4b23a2e8e971876d075d3ae322754dbc0495413d by jano.vesely
libclc: Move rsqrt implementation to a .cl file

Reviewer: awatry
Differential Revision: https://reviews.llvm.org/D74013
The file was modifiedlibclc/generic/lib/SOURCES
The file was addedlibclc/generic/lib/math/rsqrt.cl
The file was modifiedlibclc/generic/include/clc/math/rsqrt.h
Commit 85e2fa44c64e1edd2f675c990ecc60f5fadb4686 by jano.vesely
libclc/r600: Use target specific builtins to implement rsqrt and native_rsqrt

Fixes OCL CTS rsqrt and half_rsqrt (1 thread, scalaer) tests on AMD Turks.

Reviewer: awatry
Differential Revision: https://reviews.llvm.org/D74016
The file was addedlibclc/r600/lib/math/native_rsqrt.cl
The file was modifiedlibclc/r600/lib/SOURCES
The file was addedlibclc/r600/lib/math/rsqrt.cl
Commit dbcc1392b3807d7ddcb000741d2ffb276d90d36b by craig.topper
[X86] Remove isel patterns that include a vselect/X86selects and a strict FP node.

A vselect+strictfp node is not equivalent to a masked operation.
The exceptions of the strictfp node are not masked by a vselect
after it so we can't match it to a masked operation.

We already had a hack in IsLegalToFold to prevent these patterns from
matching. This patch removes that hack and removes the patterns.
The file was modifiedllvm/lib/Target/X86/X86ISelDAGToDAG.cpp
The file was modifiedllvm/lib/Target/X86/X86InstrAVX512.td
Commit dd262222b403dcfc5aef8fe4c49678ac5675a276 by craig.topper
[X86] Use MVT::i32 for the type of a MOV32r0 created in X86DAGToDAGISel::Select.

Not sure if this really matters. The VT isn't really used after
this point. At best it might affect CSE.
The file was modifiedllvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Commit e82e17d4d4cac8b2df00094e80d5e1cb22795664 by llvm-dev
[X86] Add lowerShuffleAsBitRotate (PR44379)

As noted on PR44379, we didn't attempt to lower vector shuffles using bit rotations on XOP/AVX512F targets.

This patch lowers to uniform ISD:ROTL nodes - ROTR isn't supported by XOP and they are interchangeable for constant values anyway.

There might be cases where targets without ISD:ROTL support would benefit from this (expanding to SRL+SHL+OR), which I'll investigate in a future patch.

Also, non-AVX512BW targets fail to concatenate 256-bit rotations back to 512-bits (split during shuffle lowering as they don't have v32i16/v64i8 types).
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-256-v16.ll
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-512-v32.ll
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-512-v64.ll
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-128-v16.ll
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-128-v8.ll
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-256-v32.ll
Commit e1cbfecdb866211a8f4f51064e96c200b278232b by craig.topper
[X86] Add flag result VT to a MOV32r0 created in X86DAGToDAGISel::Select

The flag isn't used, but I believe this matches the MOV32r0 that
would be created by the table emitter. This should allow this node
to be CSEed with any others created by the table.
The file was modifiedllvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Commit 656d66f5fc51ce6003b1ef114d6806168fb1f159 by craig.topper
[X86] Use custom isel for (X86sbb_flag 0, 0) so we can use 32-bit SBB for i8/i16.

We were using MOV32r0 and an extract_subreg as an input. By using
custom isel we can move the extract_subreg to after the SBB instead
of on the input.
The file was modifiedllvm/lib/Target/X86/X86ISelDAGToDAG.cpp
The file was modifiedllvm/lib/Target/X86/X86InstrCompiler.td
The file was modifiedllvm/test/CodeGen/X86/shl-crash-on-legalize.ll
Commit 29e646fe655cb63a23a08e7213599e51ef564ab5 by llvm-dev
[X86] combineConcatVectorOps - combine VROTLI/VROTRI ops

Fix issue mentioned on rGe82e17d4d4ca - non-AVX512BW targets failed to concatenate 256-bit rotations back to 512-bits (split during shuffle lowering as they don't have v32i16/v64i8 types).
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-512-v64.ll
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-512-v32.ll
Commit 6e1770821fbd05bd5180530aca17e1455d1c29d8 by arsenm2
AMDGPU: Fix SI_IF lowering when the save exec reg has terminator uses

Reverts part of 6524a7a2b9ca072bd7f7b4355d1230e70c679d2f. Since that
commit, the expansion was ignoring the actual save exec register
produced by the instruction, and looking at other instructions. I do
not understand why it was looking at other instructions, but relying
on this scan was wrong.

Fixes verifier errors after SI_IF is tail duplicated, which should be
correct to do. The results were fed into a phi, which was lowered to
the S_MOV_B64_term instructions.
The file was modifiedllvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
The file was addedllvm/test/CodeGen/AMDGPU/si-if-lower-user-terminators.mir
Commit 00115d767f34ecab35f86c29f37593efadd2b327 by arsenm2
AMDGPU: Remove dead kill handling

At one point a custom node was used for kill handling, but now the
intrinsic is directly selected. Remove leftover pattern machinery.
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
The file was modifiedllvm/lib/Target/AMDGPU/SIInstructions.td
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td
Commit f4a38c114e124c21549d06281554658687012179 by arsenm2
AMDGPU/GlobalISel: Look through casts when legalizing vector indexing

We were failing to find constants that were casted. I feel like the
artifact combiner should have folded the constant in the trunc before
the custom lowering, but that doesn't happen.
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert-vector-elt.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
Commit 2126c70e3a628cb772d7b9f63cb897857214245a by arsenm2
AMDGPU/GlobalISel: Don't mis-select vector index on a constant

Vector indexing with a constant index should be folded out in the
legalizer, but this was accidentally falling through. This would
produce the indexing operation with $noreg. Handle this case as a
dynamic index just in case a bug like this happens again in the
future.
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert-vector-elt.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extract-vector-elt.mir
Commit 6135f5eda48eb12a98f835d976e4916cfd44764c by arsenm2
GlobalISel: Fix narrowing of G_CTLZ/G_CTTZ

The result type is separate from the source type.
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/legalizer/cttz.mir
The file was modifiedllvm/lib/Target/Mips/MipsLegalizerInfo.cpp
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/legalizer/ctlz.mir
The file was modifiedllvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp
The file was modifiedllvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
Commit c437f6c6873fe32e99e975f4fb1fe3b3531cb93c by arsenm2
AMDGPU/GlobalISel: Split 64-bit G_CTPOP in RegBankSelect
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctpop.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
Commit 312a9d1b8343f5185ae9c6cdd2b022f1f93514e5 by arsenm2
GlobalISel: Fix narrowScalar for G_{CTLZ|CTTZ}_ZERO_UNDEF

Narrow these for 64-bit VALU for AMDGPU.
The file was modifiedllvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-cttz-zero-undef.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctlz-zero-undef.mir
Commit 512c03bac449d8d40c5fc8d0ff1719f887c7fdc3 by maskray
[DebugInfo] Add a DWARFDataExtractor constructor that takes ArrayRef<uint8_t>

Similar to D67797 (DataExtractor).
The file was modifiedlldb/source/Plugins/SymbolFile/DWARF/DWARFDataExtractor.cpp
The file was modifiedllvm/tools/llvm-readobj/DwarfCFIEHPrinter.h
The file was modifiedllvm/lib/DebugInfo/DWARF/DWARFDebugLoc.cpp
The file was modifiedlldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.cpp
The file was modifiedllvm/include/llvm/DebugInfo/DWARF/DWARFDataExtractor.h
Commit 64f417200e1020305f28f3c1e40691585f50f6ad by shiva0217
[RISCV] Fix incorrect FP base CFI offset for variable argument functions

When the FP exists, the FP base CFI directive offset should take the size of variable arguments into account.

Differential Revision: https://reviews.llvm.org/D73862
The file was modifiedllvm/test/CodeGen/RISCV/vararg.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVFrameLowering.cpp
Commit 05d44204fa13767a366c37695c2131161158ea36 by craig.topper
[X86] Use MOVZX instead of MOVSX in f16_to_fp isel patterns.

Using sign extend forces the adjacent element to either all zeros
or all ones. But all ones is a NAN. So that doesn't seem like a
great idea.

Trying to work on supporting this with strict FP where NAN would
definitely be bad.
The file was modifiedllvm/test/CodeGen/X86/vec_fp_to_int.ll
The file was modifiedllvm/test/CodeGen/X86/pr31088.ll
The file was modifiedllvm/test/CodeGen/X86/vector-half-conversions.ll
The file was modifiedllvm/lib/Target/X86/X86InstrSSE.td
The file was modifiedllvm/lib/Target/X86/X86InstrAVX512.td
The file was modifiedllvm/test/CodeGen/X86/avx512-vec-cmp.ll
The file was modifiedllvm/test/CodeGen/X86/half.ll
The file was modifiedllvm/test/CodeGen/X86/avx512-insert-extract.ll
Commit f24c43c0c50f2b89f6ce74bcdb0b24a8d73d4cc6 by craig.topper
[X86] Autogenerate complete checks. NFC
The file was modifiedllvm/test/CodeGen/X86/fastmath-float-half-conversion.ll
Commit a06789138987d1f64bb2f97d3a5c0f39eaf94715 by michael.hliao
[clang][codegen] Fix another lifetime emission on alloca on non-default address space.

- Lifetime intrinsics expect the pointer directly from alloca. Need
  extra handling for targets with alloca on non-default (or non-zero)
  address space.
The file was modifiedclang/lib/CodeGen/CGCall.cpp
The file was modifiedclang/lib/CodeGen/CodeGenFunction.h
The file was addedclang/test/CodeGenCXX/amdgcn-call-with-aggarg.cpp
Commit ab3da5dd66c0fee4f6ecbaf344c5904323ac7c7d by michael.hliao
Fix `-Wparentheses` warning. NFC.
The file was modifiedllvm/lib/Transforms/IPO/OpenMPOpt.cpp
Commit 06ba969c9dc98ba4d40d6e6c13822e2752aaffc5 by craig.topper
[X86] Make (insert_vector_elt (v8i16 zerovec), i16 %x, 0) generate the same code as (v8i16 (build_vector %x, 0, 0, 0, 0, 0, 0, 0)).

Instead of using a insrw to element 0, use movzx and movd.

Same for v16i8.
The file was modifiedllvm/test/CodeGen/X86/avx512-intrinsics-upgrade.ll
The file was modifiedllvm/test/CodeGen/X86/broadcastm-lowering.ll
The file was modifiedllvm/test/CodeGen/X86/merge-consecutive-loads-256.ll
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/vec_cast.ll
The file was modifiedllvm/test/CodeGen/X86/avx512bwvl-intrinsics-upgrade.ll
The file was modifiedllvm/test/CodeGen/X86/vector-mulfix-legalize.ll
The file was modifiedllvm/test/CodeGen/X86/avx512vl-intrinsics-upgrade.ll
The file was modifiedllvm/test/CodeGen/X86/buildvec-insertvec.ll
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-128-v16.ll
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-variable-128.ll
Commit d0749cc709d9e432e9ff6e861f45c6bd92acaadf by johannes
[Attributor][NFC] Use existing constant instead of magic one
The file was modifiedllvm/include/llvm/Transforms/IPO/Attributor.h
Commit 103364b4b23e37fff66f2da37873cfd890f9a4e5 by johannes
[Attributor][Tests][NFC] Add more range tests

Inspired by https://llvm.discourse.group/t/impossible-condition-optimization/461
The file was modifiedllvm/test/Transforms/Attributor/range.ll
Commit d0a6b32b4fa575b21ad4ba9407a227828e68cf39 by craig.topper
[X86] Autogenerate complete checks. NFC
The file was modifiedllvm/test/CodeGen/X86/cvt16.ll
Commit 028db8c490bb29fb2fb7fab63771e72923d275fa by johannes
[Attributor][FIX] Call right base method in AAValueConstantRangeFloating

We now call the base class method as we should.
The file was modifiedllvm/test/Transforms/Attributor/range.ll
The file was modifiedllvm/lib/Transforms/IPO/Attributor.cpp
Commit ffdbd2a06ca2a2703647fb87140b8965b3b0218c by johannes
[Attributor] Look through (some) casts in AAValueConstantRangeFloating

Casts can be handled natively by the ConstantRange class. We do limit it
to extends for now as we assume an integer type in different locations.
A TODO and a test case with a FIXME was added to remove that restriction
in the future.
The file was modifiedllvm/lib/Transforms/IPO/Attributor.cpp
The file was modifiedllvm/test/Transforms/Attributor/IPConstantProp/PR16052.ll
The file was modifiedllvm/test/Transforms/Attributor/range.ll
Commit 7e7e6594b3450dbdaffbbeb39e832f6f39ce45a9 by johannes
[Attributor] Allow SelectInst in AAValueConstantRangeFloating

The genericValueTraversal will already handle SelectInst properly and we
just needed to allow them in the initialize method.
The file was modifiedllvm/test/Transforms/Attributor/range.ll
The file was modifiedllvm/lib/Transforms/IPO/Attributor.cpp
Commit 63adbb9a0ed9a40fc47c72502754d88d04ede1e0 by johannes
[Attributor][FIX] Remove FIXME that seems outdated

The change is performed as stated by the FIXME and the tests are
adjusted. All changes look fine to me and values can be inferred as
undef without it being an error.
The file was modifiedllvm/test/Transforms/Attributor/dereferenceable-1.ll
The file was modifiedllvm/test/Transforms/Attributor/IPConstantProp/PR16052.ll
The file was modifiedllvm/test/Transforms/Attributor/undefined_behavior.ll
The file was modifiedllvm/lib/Transforms/IPO/Attributor.cpp
Commit 8155439331ac8f85be54adbd053c100567927d7c by johannes
[Attributor] Allow PHI nodes in AAValueConstantRangeFloating

Traversing PHI nodes is natural with the genericValueTraversal but also
a bit tricky. The problem is similar to the ones we have seen in AAAlign
and AADereferenceable, namely that we continue to increase the range in
each iteration. We use a pessimistic approach here to stop the
iterations. Nevertheless, optimistic information can now be propagated
through a PHI node.
The file was modifiedllvm/test/Transforms/Attributor/liveness.ll
The file was modifiedllvm/test/Transforms/Attributor/range.ll
The file was modifiedllvm/lib/Transforms/IPO/Attributor.cpp
The file was modifiedllvm/test/Transforms/Attributor/willreturn.ll
Commit 21c9d9ad43f07c07a127bc6f29f13f62e831ab11 by Amara Emerson
[GlobalISel][CallLowering] Tighten constantexpr check for callee.

I'm not sure there's a test case for this, but it's better to be safe.
The file was modifiedllvm/lib/CodeGen/GlobalISel/CallLowering.cpp
Commit d180899cb7107fdee4078f890cc18ea635925c09 by djordje.todorovic
[llvm-dwarfdump][Stats] Fix the License header

Fix the added License.

Differential Revision: https://reviews.llvm.org/D74207
The file was modifiedllvm/tools/llvm-dwarfdump/Statistics.cpp
Commit 1c0ebcca6edd977194efbccb7b6c35777439bcd3 by johannes
[Attributor][Tests] Run the CGSCC versions on the range.ll test
The file was modifiedllvm/test/Transforms/Attributor/range.ll
Commit 87ddf1f4fad01bccb70f10a3ee5c5ad5b20e4de4 by johannes
[Attributor] Simple casts preserve no-alias property

This is a minimal but important advancement over the existing code. A
cast with an operand that is only used in the cast retains the no-alias
property of the operand.
The file was modifiedllvm/test/Transforms/Attributor/noalias.ll
The file was modifiedllvm/lib/Transforms/IPO/Attributor.cpp
Commit d2e434a46107b3f191c1dffddd52fc04a50b8460 by johannes
[Attributor][FIX] Make check lines explicit

There is a bug in `update_test_checks.py` that combines check lines it
should not. For now we unbreak the bots by making all possibilities
explicit.
The file was modifiedllvm/test/Transforms/Attributor/range.ll
Commit 8756869170e67019151bff0fc7657597f37fced2 by sebastian.neubauer
[AMDGPU] Add a16 feature to gfx10

Based on D72931

This adds a new feature called A16 which is enabled for gfx10.
gfx9 keeps the R128A16 feature so it can share all the instruction encodings
with gfx7/8.

Differential Revision: https://reviews.llvm.org/D73956
The file was modifiedllvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.a16.dim.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPU.td
The file was modifiedllvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.load.a16.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/nsa-vmem-hazard.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.store.a16.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrFormats.td
The file was modifiedllvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
The file was modifiedllvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
The file was modifiedllvm/lib/Target/AMDGPU/MIMGInstructions.td
The file was modifiedllvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.store.a16.d16.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.td
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.load.a16.d16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.a16.dim.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/mcp-overlap-after-propagation.mir
The file was addedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.a16.encode.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.a16.dim.ll
The file was modifiedllvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h
Commit ea2af727a5c38906e3d1321de51aaa126b4efc69 by Raphael Isemann
[lldb] Refactored TestCallOverriddenMethod.py to general virtual function test

This actually tests all the different situations in which we can call virtual
functions. This removes also all skipIfs as the first skipIf for Linux is
apparently fixed and the second skipIf was just failing due to the constructor
call (which should be its own test and not be tested here).
The file was removedlldb/packages/Python/lldbsuite/test/lang/cpp/overriden-methods/Makefile
The file was removedlldb/packages/Python/lldbsuite/test/lang/cpp/overriden-methods/TestCallOverriddenMethod.py
The file was removedlldb/packages/Python/lldbsuite/test/lang/cpp/overriden-methods/main.cpp
The file was addedlldb/packages/Python/lldbsuite/test/lang/cpp/virtual-functions/TestCppVirtualFunctions.py
The file was addedlldb/packages/Python/lldbsuite/test/lang/cpp/virtual-functions/main.cpp
The file was addedlldb/packages/Python/lldbsuite/test/lang/cpp/virtual-functions/Makefile
Commit d2e0fee77bc82a54bcc11ce778ce12f068f9e326 by jan.kratochvil
[lldb] [doc] Change sample commands prefix from > to $

Remove all beginning > from the sample commands as my accidental
copy-paste (multiple times...) will discard ./bin/llvm-lit which is
difficult to rebuild (I have to rm -rf and cmake it all again).

Differential Revision: https://reviews.llvm.org/D74296
The file was modifiedlldb/docs/resources/test.rst
Commit 68908993ebd2af459cd0f2ed6ab340bf62fb3e9d by djordje.todorovic
[CSInfo] Use isCandidateForCallSiteEntry() when updating the CSInfo

Use the isCandidateForCallSiteEntry().
This should mostly be an NFC, but there are some parts ensuring
the moveCallSiteInfo() and copyCallSiteInfo() operate with call site
entry candidates (both Src and Dest should be the call site entry
candidates).

Differential Revision: https://reviews.llvm.org/D74122
The file was modifiedllvm/lib/CodeGen/InlineSpiller.cpp
The file was modifiedllvm/lib/CodeGen/LiveRangeEdit.cpp
The file was modifiedllvm/lib/CodeGen/MachineOutliner.cpp
The file was modifiedllvm/lib/CodeGen/IfConversion.cpp
The file was modifiedllvm/lib/Target/X86/X86ExpandPseudo.cpp
The file was modifiedllvm/lib/CodeGen/TargetInstrInfo.cpp
The file was modifiedllvm/lib/CodeGen/UnreachableBlockElim.cpp
The file was modifiedllvm/lib/CodeGen/MachineFunction.cpp
The file was modifiedllvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
The file was modifiedllvm/lib/CodeGen/BranchFolding.cpp
The file was modifiedllvm/lib/CodeGen/PeepholeOptimizer.cpp
The file was modifiedllvm/lib/CodeGen/XRayInstrumentation.cpp
Commit a5040d5ec97ecac9940275eb59175f0bdbd26ab4 by kai
[SytemZ] Disable vector ABI when using option -march=arch[8|9|10]

When specifying -march=arch[8|9|10], those CPU types do NOT support
the vector extension. In this case the vector ABI must be disabled.
The generated data layout should NOT contain 64-v128.

Reviewers: uweigand

Differential Revision: https://reviews.llvm.org/D74146
The file was modifiedllvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
The file was modifiedclang/test/CodeGen/target-data.c
Commit 6115bd9ba2851469d372d0d7b36d87a3e1d8094b by martin
[LLDB] Fix GCC warnings about extra semicolons. NFC.
The file was modifiedlldb/source/Plugins/ABI/Mips/ABISysV_mips.cpp
The file was modifiedlldb/source/Plugins/Platform/Windows/PlatformWindows.cpp
The file was modifiedlldb/source/Plugins/ABI/Mips/ABISysV_mips64.cpp
The file was modifiedlldb/source/Plugins/ABI/AArch64/ABISysV_arm64.cpp
The file was modifiedlldb/source/Plugins/Platform/NetBSD/PlatformNetBSD.cpp
The file was modifiedlldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.cpp
The file was modifiedlldb/source/Plugins/InstrumentationRuntime/MainThreadChecker/InstrumentationRuntimeMainThreadChecker.cpp
The file was modifiedlldb/source/Plugins/UnwindAssembly/x86/UnwindAssembly-x86.cpp
The file was modifiedlldb/source/Plugins/ABI/X86/ABIWindows_x86_64.cpp
The file was modifiedlldb/source/Plugins/ObjectFile/Breakpad/ObjectFileBreakpad.cpp
The file was modifiedlldb/source/Plugins/Process/elf-core/ProcessElfCore.cpp
The file was modifiedlldb/source/Plugins/DynamicLoader/MacOSX-DYLD/DynamicLoaderMacOS.cpp
The file was modifiedlldb/source/Plugins/SymbolFile/Symtab/SymbolFileSymtab.cpp
The file was modifiedlldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
The file was modifiedlldb/source/Plugins/ABI/AArch64/ABIMacOSX_arm64.cpp
The file was modifiedlldb/source/Plugins/ABI/X86/ABISysV_x86_64.cpp
The file was modifiedlldb/source/Plugins/Platform/Linux/PlatformLinux.cpp
The file was modifiedlldb/source/Plugins/SymbolVendor/wasm/SymbolVendorWasm.cpp
The file was modifiedlldb/source/Plugins/ObjectContainer/BSD-Archive/ObjectContainerBSDArchive.cpp
The file was modifiedlldb/source/Plugins/Platform/OpenBSD/PlatformOpenBSD.cpp
The file was modifiedlldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDebugMap.cpp
The file was modifiedlldb/source/Plugins/Platform/MacOSX/PlatformMacOSX.cpp
The file was modifiedlldb/source/Plugins/SymbolVendor/MacOSX/SymbolVendorMacOSX.cpp
The file was modifiedlldb/source/Plugins/Platform/MacOSX/PlatformRemoteiOS.cpp
The file was modifiedlldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
The file was modifiedlldb/source/Plugins/JITLoader/GDB/JITLoaderGDB.cpp
The file was modifiedlldb/source/Plugins/SymbolFile/PDB/SymbolFilePDB.cpp
The file was modifiedlldb/source/Plugins/InstrumentationRuntime/ASan/InstrumentationRuntimeASan.cpp
The file was modifiedlldb/source/Plugins/Process/Windows/Common/ProcessWindows.cpp
The file was modifiedlldb/source/Plugins/LanguageRuntime/CPlusPlus/ItaniumABI/ItaniumABILanguageRuntime.cpp
The file was modifiedlldb/source/Plugins/ObjectFile/PECOFF/ObjectFilePECOFF.cpp
The file was modifiedlldb/source/Plugins/Process/mach-core/ProcessMachCore.cpp
The file was modifiedlldb/source/Plugins/InstrumentationRuntime/UBSan/InstrumentationRuntimeUBSan.cpp
The file was modifiedlldb/source/Plugins/Architecture/PPC64/ArchitecturePPC64.cpp
The file was modifiedlldb/source/Plugins/Language/ObjCPlusPlus/ObjCPlusPlusLanguage.cpp
The file was modifiedlldb/source/Plugins/ScriptInterpreter/None/ScriptInterpreterNone.cpp
The file was modifiedlldb/source/Plugins/ABI/SystemZ/ABISysV_s390x.cpp
The file was modifiedlldb/source/Plugins/Architecture/Mips/ArchitectureMips.cpp
The file was modifiedlldb/source/Plugins/ABI/PowerPC/ABISysV_ppc64.cpp
The file was modifiedlldb/source/Plugins/ABI/ARM/ABIMacOSX_arm.cpp
The file was modifiedlldb/source/Plugins/LanguageRuntime/RenderScript/RenderScriptRuntime/RenderScriptRuntime.cpp
The file was modifiedlldb/source/Plugins/ABI/PowerPC/ABISysV_ppc.cpp
The file was modifiedlldb/source/Plugins/ObjectFile/wasm/ObjectFileWasm.cpp
The file was modifiedlldb/source/Plugins/Process/FreeBSD/ProcessFreeBSD.cpp
The file was modifiedlldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
The file was modifiedlldb/source/Plugins/SymbolVendor/ELF/SymbolVendorELF.cpp
The file was modifiedlldb/source/Plugins/Instruction/ARM64/EmulateInstructionARM64.cpp
The file was modifiedlldb/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp
The file was modifiedlldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp
The file was modifiedlldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp
The file was modifiedlldb/source/Plugins/MemoryHistory/asan/MemoryHistoryASan.cpp
The file was modifiedlldb/source/Plugins/DynamicLoader/Static/DynamicLoaderStatic.cpp
The file was modifiedlldb/source/Plugins/Platform/Android/PlatformAndroid.cpp
The file was modifiedlldb/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
The file was modifiedlldb/source/Plugins/ABI/X86/ABISysV_i386.cpp
The file was modifiedlldb/source/Plugins/Process/minidump/ProcessMinidump.cpp
The file was modifiedlldb/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp
The file was modifiedlldb/source/Plugins/DynamicLoader/MacOSX-DYLD/DynamicLoaderMacOSXDYLD.cpp
The file was modifiedlldb/source/Plugins/Platform/gdb-server/PlatformRemoteGDBServer.cpp
The file was modifiedlldb/source/Plugins/DynamicLoader/Windows-DYLD/DynamicLoaderWindowsDYLD.cpp
The file was modifiedlldb/source/Plugins/DynamicLoader/POSIX-DYLD/DynamicLoaderPOSIXDYLD.cpp
The file was modifiedlldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCRuntime.cpp
The file was modifiedlldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
The file was modifiedlldb/source/Plugins/InstrumentationRuntime/TSan/InstrumentationRuntimeTSan.cpp
The file was modifiedlldb/source/Plugins/Instruction/PPC64/EmulateInstructionPPC64.cpp
The file was modifiedlldb/source/Plugins/UnwindAssembly/InstEmulation/UnwindAssemblyInstEmulation.cpp
The file was modifiedlldb/source/Plugins/ABI/Hexagon/ABISysV_hexagon.cpp
The file was modifiedlldb/source/Plugins/Language/ObjC/ObjCLanguage.cpp
The file was modifiedlldb/source/Plugins/DynamicLoader/Darwin-Kernel/DynamicLoaderDarwinKernel.cpp
The file was modifiedlldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp
The file was modifiedlldb/source/Plugins/ABI/X86/ABIMacOSX_i386.cpp
The file was modifiedlldb/source/Plugins/Platform/FreeBSD/PlatformFreeBSD.cpp
The file was modifiedlldb/source/Plugins/SymbolFile/Breakpad/SymbolFileBreakpad.cpp
The file was modifiedlldb/source/Plugins/ABI/ARC/ABISysV_arc.cpp
The file was modifiedlldb/source/Plugins/ABI/ARM/ABISysV_arm.cpp
The file was modifiedlldb/source/Plugins/SystemRuntime/MacOSX/SystemRuntimeMacOSX.cpp
The file was modifiedlldb/source/Plugins/ObjectContainer/Universal-Mach-O/ObjectContainerUniversalMachO.cpp
The file was modifiedlldb/source/Plugins/ScriptInterpreter/Lua/ScriptInterpreterLua.cpp
The file was modifiedlldb/source/Plugins/OperatingSystem/Python/OperatingSystemPython.cpp
The file was modifiedlldb/source/Plugins/Architecture/Arm/ArchitectureArm.cpp
The file was modifiedlldb/source/Plugins/StructuredData/DarwinLog/StructuredDataDarwinLog.cpp
The file was modifiedlldb/source/Plugins/Process/MacOSX-Kernel/ProcessKDP.cpp