FailedChanges

Summary

  1. [ARM] WLS/LE Code Generation Backend changes to enable WLS/LE low-overhead loops for armv8.1-m: 1) Use TTI to communicate to the HardwareLoop pass that we should try to generate intrinsics that guard the loop entry, as well as setting the loop trip count. 2) Lower the BRCOND that uses said intrinsic to an Arm specific node: ARMWLS. 3) ISelDAGToDAG the node to a new pseudo instruction: t2WhileLoopStart. 4) Add support in ArmLowOverheadLoops to handle the new pseudo instruction. Differential Revision: https://reviews.llvm.org/D63816
  2. [libcxx] [test] Add void cast to result of compare_exchange_weak to suppress [[nodiscard]].
  3. [clangd] Make FixIt message be consistent with the clang-tidy diagnostic message. Summary: We strip the "[clang-tidy-check]" suffix from the clang-tidy diagnostics, we should be consistent with the message in FixIt (strip the suffix as well). Reviewers: sammccall Subscribers: ilya-biryukov, MaskRay, jkorous, arphaman, kadircet, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D63926
  4. [X86] Add more load folding tests for vcvt(t)ps2(u)qq showing missed foldings. NFC
  5. [X86] Improve the type checking fast-isel handling of vector bitcasts. We had a bunch of vector size legality checks for the source type based on feature flags, but we didn't check the destination type at all beyond ensuring that it was a "simple" type. But this allowed the destination to be i128 which isn't legal. This commit changes the code to use TLI's isTypeLegal logic in place of the all the subtarget checks. Then additionally checks that the source and dest are vectors. Fixes 42452
  6. [X86] Add a DAG combine to replace vector loads feeding a v4i32->v2f64 CVTSI2FP/CVTUI2FP node with a vzload. But only when the load isn't volatile. This improves load folding during isel where we only have vzload and scalar_to_vector+load patterns. We can't have full vector load isel patterns for the same volatile load issue. Also add some missing masked cvtsi2fp/cvtui2fp with vzload patterns.
  7. [X86] Add some additional load folding tests to vec_int_to_fp.ll/vec_int_to_fp-widen.ll and disable the peephole pass. Also copy some missing test cases from vec_int_to_fp.ll to vec_int_to_fp-widen.ll
  8. [X86] Add MOVHPDrm/MOVLPDrm patterns that use VZEXT_LOAD. We already had patterns that used scalar_to_vector+load. But we can also have a vzload. Found while investigating combining scalar_to_vector+load to vzload.
Revision 364733 by sam_parker:
[ARM] WLS/LE Code Generation
   
Backend changes to enable WLS/LE low-overhead loops for armv8.1-m:
1) Use TTI to communicate to the HardwareLoop pass that we should try
   to generate intrinsics that guard the loop entry, as well as setting
   the loop trip count.
2) Lower the BRCOND that uses said intrinsic to an Arm specific node:
   ARMWLS.
3) ISelDAGToDAG the node to a new pseudo instruction:
   t2WhileLoopStart.
4) Add support in ArmLowOverheadLoops to handle the new pseudo
   instruction.

Differential Revision: https://reviews.llvm.org/D63816
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/CodeGen/HardwareLoops.cpp (diff)llvm.src/lib/CodeGen/HardwareLoops.cpp
The file was modified/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (diff)llvm.src/lib/Target/ARM/ARMISelDAGToDAG.cpp
The file was modified/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (diff)llvm.src/lib/Target/ARM/ARMISelLowering.cpp
The file was modified/llvm/trunk/lib/Target/ARM/ARMISelLowering.h (diff)llvm.src/lib/Target/ARM/ARMISelLowering.h
The file was modified/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (diff)llvm.src/lib/Target/ARM/ARMInstrInfo.td
The file was modified/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (diff)llvm.src/lib/Target/ARM/ARMInstrThumb2.td
The file was modified/llvm/trunk/lib/Target/ARM/ARMLowOverheadLoops.cpp (diff)llvm.src/lib/Target/ARM/ARMLowOverheadLoops.cpp
The file was modified/llvm/trunk/lib/Target/ARM/ARMTargetTransformInfo.cpp (diff)llvm.src/lib/Target/ARM/ARMTargetTransformInfo.cpp
The file was added/llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoopsllvm.src/test/CodeGen/Thumb2/LowOverheadLoops
The file was added/llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/cond-mov.mirllvm.src/test/CodeGen/Thumb2/LowOverheadLoops/cond-mov.mir
The file was added/llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/loop-guards.llllvm.src/test/CodeGen/Thumb2/LowOverheadLoops/loop-guards.ll
The file was added/llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/massive.mirllvm.src/test/CodeGen/Thumb2/LowOverheadLoops/massive.mir
The file was added/llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/multiblock-massive.mirllvm.src/test/CodeGen/Thumb2/LowOverheadLoops/multiblock-massive.mir
The file was added/llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-call.mirllvm.src/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-call.mir
The file was added/llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-spill.mirllvm.src/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-spill.mir
The file was added/llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/revert-while.mirllvm.src/test/CodeGen/Thumb2/LowOverheadLoops/revert-while.mir
The file was added/llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/size-limit.mirllvm.src/test/CodeGen/Thumb2/LowOverheadLoops/size-limit.mir
The file was added/llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/switch.mirllvm.src/test/CodeGen/Thumb2/LowOverheadLoops/switch.mir
The file was added/llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/while.mirllvm.src/test/CodeGen/Thumb2/LowOverheadLoops/while.mir
The file was removed/llvm/trunk/test/Transforms/HardwareLoops/ARM/cond-mov.mirllvm.src/test/Transforms/HardwareLoops/ARM/cond-mov.mir
The file was modified/llvm/trunk/test/Transforms/HardwareLoops/ARM/do-rem.ll (diff)llvm.src/test/Transforms/HardwareLoops/ARM/do-rem.ll
The file was modified/llvm/trunk/test/Transforms/HardwareLoops/ARM/fp-emulation.ll (diff)llvm.src/test/Transforms/HardwareLoops/ARM/fp-emulation.ll
The file was removed/llvm/trunk/test/Transforms/HardwareLoops/ARM/massive.mirllvm.src/test/Transforms/HardwareLoops/ARM/massive.mir
The file was removed/llvm/trunk/test/Transforms/HardwareLoops/ARM/multiblock-massive.mirllvm.src/test/Transforms/HardwareLoops/ARM/multiblock-massive.mir
The file was removed/llvm/trunk/test/Transforms/HardwareLoops/ARM/revert-after-call.mirllvm.src/test/Transforms/HardwareLoops/ARM/revert-after-call.mir
The file was removed/llvm/trunk/test/Transforms/HardwareLoops/ARM/revert-after-spill.mirllvm.src/test/Transforms/HardwareLoops/ARM/revert-after-spill.mir
The file was modified/llvm/trunk/test/Transforms/HardwareLoops/ARM/simple-do.ll (diff)llvm.src/test/Transforms/HardwareLoops/ARM/simple-do.ll
The file was removed/llvm/trunk/test/Transforms/HardwareLoops/ARM/size-limit.mirllvm.src/test/Transforms/HardwareLoops/ARM/size-limit.mir
The file was modified/llvm/trunk/test/Transforms/HardwareLoops/ARM/structure.ll (diff)llvm.src/test/Transforms/HardwareLoops/ARM/structure.ll
The file was removed/llvm/trunk/test/Transforms/HardwareLoops/ARM/switch.mirllvm.src/test/Transforms/HardwareLoops/ARM/switch.mir
Revision 364732 by bion:
[libcxx] [test] Add void cast to result of compare_exchange_weak to suppress [[nodiscard]].
Change TypePath in RepositoryPath in Workspace
The file was modified/libcxx/trunk/test/std/atomics/atomics.general/replace_failure_order.pass.cpp (diff)libcxx.src/test/std/atomics/atomics.general/replace_failure_order.pass.cpp
Revision 364731 by hokein:
[clangd] Make FixIt message be consistent with the clang-tidy diagnostic message.

Summary:
We strip the "[clang-tidy-check]" suffix from the clang-tidy diagnostics, we
should be consistent with the message in FixIt (strip the suffix as well).

Reviewers: sammccall

Subscribers: ilya-biryukov, MaskRay, jkorous, arphaman, kadircet, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D63926
Change TypePath in RepositoryPath in Workspace
The file was modified/clang-tools-extra/trunk/clangd/Diagnostics.cpp (diff)clang-tools-extra.src/clangd/Diagnostics.cpp
The file was modified/clang-tools-extra/trunk/clangd/unittests/DiagnosticsTests.cpp (diff)clang-tools-extra.src/clangd/unittests/DiagnosticsTests.cpp
Revision 364730 by ctopper:
[X86] Add more load folding tests for vcvt(t)ps2(u)qq showing missed foldings. NFC
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/CodeGen/X86/avx512dqvl-intrinsics.ll (diff)llvm.src/test/CodeGen/X86/avx512dqvl-intrinsics.ll
The file was modified/llvm/trunk/test/CodeGen/X86/vec_fp_to_int-widen.ll (diff)llvm.src/test/CodeGen/X86/vec_fp_to_int-widen.ll
The file was modified/llvm/trunk/test/CodeGen/X86/vec_fp_to_int.ll (diff)llvm.src/test/CodeGen/X86/vec_fp_to_int.ll
Revision 364729 by ctopper:
[X86] Improve the type checking fast-isel handling of vector bitcasts.

We had a bunch of vector size legality checks for the source type
based on feature flags, but we didn't check the destination type at
all beyond ensuring that it was a "simple" type. But this allowed
the destination to be i128 which isn't legal.

This commit changes the code to use TLI's isTypeLegal logic in
place of the all the subtarget checks. Then additionally checks
that the source and dest are vectors.

Fixes 42452
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86FastISel.cpp (diff)llvm.src/lib/Target/X86/X86FastISel.cpp
The file was added/llvm/trunk/test/CodeGen/X86/pr42452.llllvm.src/test/CodeGen/X86/pr42452.ll
Revision 364728 by ctopper:
[X86] Add a DAG combine to replace vector loads feeding a v4i32->v2f64 CVTSI2FP/CVTUI2FP node with a vzload.

But only when the load isn't volatile.

This improves load folding during isel where we only have vzload
and scalar_to_vector+load patterns. We can't have full vector load
isel patterns for the same volatile load issue.

Also add some missing masked cvtsi2fp/cvtui2fp with vzload patterns.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (diff)llvm.src/lib/Target/X86/X86ISelLowering.cpp
The file was modified/llvm/trunk/lib/Target/X86/X86InstrAVX512.td (diff)llvm.src/lib/Target/X86/X86InstrAVX512.td
The file was modified/llvm/trunk/test/CodeGen/X86/vec_int_to_fp-widen.ll (diff)llvm.src/test/CodeGen/X86/vec_int_to_fp-widen.ll
The file was modified/llvm/trunk/test/CodeGen/X86/vec_int_to_fp.ll (diff)llvm.src/test/CodeGen/X86/vec_int_to_fp.ll
Revision 364727 by ctopper:
[X86] Add some additional load folding tests to vec_int_to_fp.ll/vec_int_to_fp-widen.ll and disable the peephole pass.

Also copy some missing test cases from vec_int_to_fp.ll to vec_int_to_fp-widen.ll
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/CodeGen/X86/vec_int_to_fp-widen.ll (diff)llvm.src/test/CodeGen/X86/vec_int_to_fp-widen.ll
The file was modified/llvm/trunk/test/CodeGen/X86/vec_int_to_fp.ll (diff)llvm.src/test/CodeGen/X86/vec_int_to_fp.ll
Revision 364726 by ctopper:
[X86] Add MOVHPDrm/MOVLPDrm patterns that use VZEXT_LOAD.

We already had patterns that used scalar_to_vector+load. But we can
also have a vzload.

Found while investigating combining scalar_to_vector+load to vzload.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86InstrAVX512.td (diff)llvm.src/lib/Target/X86/X86InstrAVX512.td
The file was modified/llvm/trunk/lib/Target/X86/X86InstrSSE.td (diff)llvm.src/lib/Target/X86/X86InstrSSE.td
The file was modified/llvm/trunk/test/CodeGen/X86/merge-consecutive-loads-128.ll (diff)llvm.src/test/CodeGen/X86/merge-consecutive-loads-128.ll