Revision
364802
by marshall:
Implement LWG2221: 'Formatted output for nullptr_t' Reviewed as: https://reviews.llvm.org/D63053 |
| Change Type | Path in Repository | Path in Workspace |
|---|
 | /libcxx/trunk/include/ostream (diff) | libcxx.src/include/ostream |
| /libcxx/trunk/test/std/input.output/iostream.format/output.streams/ostream.formatted/ostream.inserters/streambuf.pass.cpp (diff) | libcxx.src/test/std/input.output/iostream.format/output.streams/ostream.formatted/ostream.inserters/streambuf.pass.cpp |
| /libcxx/trunk/www/cxx1z_status.html (diff) | libcxx.src/www/cxx1z_status.html |
Revision
364799
by brucem:
__threading_support: Remove (void) in favor of (). Summary: This fixes a clang-tidy warning when building something that uses this file. Reviewers: mclow.lists, EricWF Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D43226 |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /libcxx/trunk/include/__threading_support (diff) | libcxx.src/include/__threading_support |
Revision
364798
by brucem:
Fix -Wdouble-promotion warnings. Reviewers: mclow.lists Subscribers: christof, ldionne, cfe-commits, libcxx-commits Differential Revision: https://reviews.llvm.org/D62782 |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /libcxx/trunk/include/limits (diff) | libcxx.src/include/limits |
| /libcxx/trunk/include/utility (diff) | libcxx.src/include/utility |
Revision
364792
by lebedevri:
[InstCombine] (Y + ~X) + 1 --> Y - X fold (PR42459) Summary: To be noted, this pattern is not unhandled by instcombine per-se, it is somehow does end up being folded when one runs opt -O3, but not if it's just -instcombine. Regardless, that fold is indirect, depends on some other folds, and is thus blind when there are extra uses. This does address the regression being exposed in D63992. https://godbolt.org/z/7DGltU https://rise4fun.com/Alive/EPO0 Fixes [[ https://bugs.llvm.org/show_bug.cgi?id=42459 | PR42459 ]] Reviewers: spatel, nikic, huihuiz Reviewed By: spatel Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D63993 |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /llvm/trunk/lib/Transforms/InstCombine/InstCombineAddSub.cpp (diff) | llvm.src/lib/Transforms/InstCombine/InstCombineAddSub.cpp |
| /llvm/trunk/test/Transforms/InstCombine/add.ll (diff) | llvm.src/test/Transforms/InstCombine/add.ll |
| /llvm/trunk/test/Transforms/InstCombine/fold-inc-of-add-of-not-x-and-y-to-sub-x-from-y.ll (diff) | llvm.src/test/Transforms/InstCombine/fold-inc-of-add-of-not-x-and-y-to-sub-x-from-y.ll |
Revision
364791
by lebedevri:
[InstCombine] Shift amount reassociation in bittest (PR42399) Summary: Given pattern: `icmp eq/ne (and ((x shift Q), (y oppositeshift K))), 0` we should move shifts to the same hand of 'and', i.e. rewrite as `icmp eq/ne (and (x shift (Q+K)), y), 0` iff `(Q+K) u< bitwidth(x)` It might be tempting to not restrict this to situations where we know we'd fold two shifts together, but i'm not sure what rules should there be to avoid endless combine loops. We pick the same shift that was originally used to shift the variable we picked to shift: https://rise4fun.com/Alive/6x1v Should fix [[ https://bugs.llvm.org/show_bug.cgi?id=42399 | PR42399]]. Reviewers: spatel, nikic, RKSimon Reviewed By: spatel Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D63829 |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp (diff) | llvm.src/lib/Transforms/InstCombine/InstCombineCompares.cpp |
| /llvm/trunk/test/Transforms/InstCombine/shift-amount-reassociation-in-bittest.ll (diff) | llvm.src/test/Transforms/InstCombine/shift-amount-reassociation-in-bittest.ll |
Revision
364790
by kparzysz:
[Hexagon] Custom-lower UADDO(x, 1) and USUBO(x, 1) |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp (diff) | llvm.src/lib/Target/Hexagon/HexagonISelLowering.cpp |
| /llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h (diff) | llvm.src/lib/Target/Hexagon/HexagonISelLowering.h |
 | /llvm/trunk/test/CodeGen/Hexagon/isel-uaddo-1.ll | llvm.src/test/CodeGen/Hexagon/isel-uaddo-1.ll |
Revision
364789
by arsenm:
AMDGPU/GlobalISel: Select G_FRAME_INDEX |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp (diff) | llvm.src/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp |
| /llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.h (diff) | llvm.src/lib/Target/AMDGPU/AMDGPUInstructionSelector.h |
| /llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-frame-index.mir | llvm.src/test/CodeGen/AMDGPU/GlobalISel/inst-select-frame-index.mir |
Revision
364788
by nha:
AMDGPU/GFX10: fix scratch resource descriptor Summary: The stride should depend on the wave size, not the hardware generation. Also, the 32_FLOAT format is 0x16, not 16; though that shouldn't be relevant. Change-Id: I088f93bf6708974d085d1c50967f119061da6dc6 Reviewers: arsenm, rampitec, mareko Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D63808 |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp (diff) | llvm.src/lib/Target/AMDGPU/SIInstrInfo.cpp |
| /llvm/trunk/test/CodeGen/AMDGPU/scratch-simple.ll (diff) | llvm.src/test/CodeGen/AMDGPU/scratch-simple.ll |
Revision
364787
by arsenm:
AMDGPU/GlobalISel: Make s16 select legal This is easy to handle and avoids legalization artifacts which are likely to obscure combines. |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp (diff) | llvm.src/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp |
| /llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp (diff) | llvm.src/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp |
| /llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-select.mir | llvm.src/test/CodeGen/AMDGPU/GlobalISel/inst-select-select.mir |
| /llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-fcmp.mir (diff) | llvm.src/test/CodeGen/AMDGPU/GlobalISel/legalize-fcmp.mir |
| /llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir (diff) | llvm.src/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir |
| /llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir (diff) | llvm.src/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir |
Revision
364786
by arsenm:
AMDGPU/GlobalISel: Select G_BRCOND for scc conditions |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp (diff) | llvm.src/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp |
| /llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.h (diff) | llvm.src/lib/Target/AMDGPU/AMDGPUInstructionSelector.h |
| /llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-br.mir | llvm.src/test/CodeGen/AMDGPU/GlobalISel/inst-select-br.mir |
| /llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-brcond.mir | llvm.src/test/CodeGen/AMDGPU/GlobalISel/inst-select-brcond.mir |
Revision
364785
by martong:
[ASTImporter] Mark erroneous nodes in shared st Summary: Now we store the errors for the Decls in the "to" context too. For that, however, we have to put these errors in a shared state (among all the ASTImporter objects which handle the same "to" context but different "from" contexts). After a series of imports from different "from" TUs we have a "to" context which may have erroneous nodes in it. (Remember, the AST is immutable so there is no way to delete a node once we had created it and we realized the error later.) All these erroneous nodes are marked in ASTImporterSharedState::ImportErrors. Clients of the ASTImporter may use this as an input. E.g. the static analyzer engine may not try to analyze a function if that is marked as erroneous (it can be queried via ASTImporterSharedState::getImportDeclErrorIfAny()). Reviewers: a_sidorin, a.sidorin, shafik Subscribers: rnkovacs, dkrupp, Szelethus, gamesh411, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D62376 |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /cfe/trunk/include/clang/AST/ASTImporter.h (diff) | clang.src/include/clang/AST/ASTImporter.h |
| /cfe/trunk/include/clang/AST/ASTImporterSharedState.h | clang.src/include/clang/AST/ASTImporterSharedState.h |
| /cfe/trunk/include/clang/CrossTU/CrossTranslationUnit.h (diff) | clang.src/include/clang/CrossTU/CrossTranslationUnit.h |
| /cfe/trunk/lib/AST/ASTImporter.cpp (diff) | clang.src/lib/AST/ASTImporter.cpp |
| /cfe/trunk/lib/CrossTU/CrossTranslationUnit.cpp (diff) | clang.src/lib/CrossTU/CrossTranslationUnit.cpp |
| /cfe/trunk/lib/Frontend/ASTMerge.cpp (diff) | clang.src/lib/Frontend/ASTMerge.cpp |
| /cfe/trunk/unittests/AST/ASTImporterFixtures.cpp (diff) | clang.src/unittests/AST/ASTImporterFixtures.cpp |
| /cfe/trunk/unittests/AST/ASTImporterFixtures.h (diff) | clang.src/unittests/AST/ASTImporterFixtures.h |
| /cfe/trunk/unittests/AST/ASTImporterTest.cpp (diff) | clang.src/unittests/AST/ASTImporterTest.cpp |
Revision
364784
by arsenm:
AMDGPU/GlobalISel: Tolerate copies with no type set isVCC has the same bug, but isn't used in a context where it can cause a problem. |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp (diff) | llvm.src/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp |
| /llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir (diff) | llvm.src/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir |
Revision
364783
by arsenm:
AMDGPU: Fix tests using the default alloca address space |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /llvm/trunk/test/CodeGen/AMDGPU/loop-idiom.ll (diff) | llvm.src/test/CodeGen/AMDGPU/loop-idiom.ll |
| /llvm/trunk/test/CodeGen/AMDGPU/unroll.ll (diff) | llvm.src/test/CodeGen/AMDGPU/unroll.ll |
Revision
364782
by arsenm:
AMDGPU/GlobalISel: Select src modifiers |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp (diff) | llvm.src/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp |
| /llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.h (diff) | llvm.src/lib/Target/AMDGPU/AMDGPUInstructionSelector.h |
| /llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcanonicalize.mir (diff) | llvm.src/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcanonicalize.mir |
| /llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.mir (diff) | llvm.src/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.mir |
Revision
364778
by rovka:
Fixup r364512 Fix stack-use-after-scope errors from r364512. One instance was already fixed in r364611 - this patch simplifies that fix and addresses one more instance of similar code. Discussed in: https://reviews.llvm.org/D63905 |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp (diff) | llvm.src/lib/CodeGen/GlobalISel/IRTranslator.cpp |
Revision
364777
by lenary:
[RISCV] Avoid save-restore target feature warning Summary: LLVM issues a warning if passed unknown target features. Neither I nor @asb noticed this until after https://reviews.llvm.org/D63498 landed. This patch stops passing the (unknown) "save-restore" target feature to the LLVM backend, but continues to emit a warning if a driver asks for `-msave-restore`. The default of assuming `-mno-save-restore` (and emitting no warnings) remains. Reviewers: asb Reviewed By: asb Subscribers: rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, cfe-commits, asb Tags: #clang Differential Revision: https://reviews.llvm.org/D64008 |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /cfe/trunk/lib/Driver/ToolChains/Arch/RISCV.cpp (diff) | clang.src/lib/Driver/ToolChains/Arch/RISCV.cpp |
| /cfe/trunk/test/Driver/riscv-features.c (diff) | clang.src/test/Driver/riscv-features.c |
Revision
364775
by jsji:
[UpdateTestChecks][PowerPC] Avoid empty string when scrubbing loop comments Summary: SCRUB_LOOP_COMMENT_RE was introduced in https://reviews.llvm.org/D31285 This works for some loops. However, we may generate lines with loop comments only. And since we don't scrub leading white spaces, this will leave an empty line there, and FileCheck will complain it. eg: llvm/test/CodeGen/PowerPC/PR35812-neg-cmpxchg.ll:27:15: error: found empty check string with prefix 'CHECK:' ; CHECK-NEXT: This prevented us from using the `update_llc_test_checks.py` for quite some cases. We should still keep the comment token there, so that we can safely scrub the loop comment without breaking FileCheck. Reviewers: timshen, hfinkel, lebedev.ri, RKSimon Subscribers: nemanjai, jfb, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D63957 |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /llvm/trunk/test/CodeGen/PowerPC/PR35812-neg-cmpxchg.ll (diff) | llvm.src/test/CodeGen/PowerPC/PR35812-neg-cmpxchg.ll |
| /llvm/trunk/utils/UpdateTestChecks/asm.py (diff) | llvm.src/utils/UpdateTestChecks/asm.py |
Revision
364774
by d0k:
[ASTImporter] Silence unused variable warning in Release builds. NFC. |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /cfe/trunk/lib/AST/ASTImporter.cpp (diff) | clang.src/lib/AST/ASTImporter.cpp |
Revision
364772
by lebedevri:
[NFC][InstCombine] Better commutative tests for "shift amount reassociation in bittest" pattern. As discussed in https://reviews.llvm.org/D63829 *if* *both* shifts are one-use, we'd most likely want to produce `lshr`, and not rely on ordering. Also, there should likely be a *separate* fold to do this reordering. |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /llvm/trunk/test/Transforms/InstCombine/shift-amount-reassociation-in-bittest.ll (diff) | llvm.src/test/Transforms/InstCombine/shift-amount-reassociation-in-bittest.ll |
Revision
364771
by martong:
[ASTImporter] Mark erroneous nodes in from ctx Summary: During import of a specific Decl D, it may happen that some AST nodes had already been created before we recognize an error. In this case we signal back the error to the caller, but the "to" context remains polluted with those nodes which had been created. Ideally, those nodes should not had been created, but that time we did not know about the error, the error happened later. Since the AST is immutable (most of the cases we can't remove existing nodes) we choose to mark these nodes as erroneous. Here are the steps of the algorithm: 1) We keep track of the nodes which we visit during the import of D: See ImportPathTy. 2) If a Decl is already imported and it is already on the import path (we have a cycle) then we copy/store the relevant part of the import path. We store these cycles for each Decl. 3) When we recognize an error during the import of D then we set up this error to all Decls in the stored cycles for D and we clear the stored cycles. Reviewers: a_sidorin, a.sidorin, shafik Subscribers: rnkovacs, dkrupp, Szelethus, gamesh411, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D62375 |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /cfe/trunk/include/clang/AST/ASTImporter.h (diff) | clang.src/include/clang/AST/ASTImporter.h |
| /cfe/trunk/lib/AST/ASTImporter.cpp (diff) | clang.src/lib/AST/ASTImporter.cpp |
| /cfe/trunk/unittests/AST/ASTImporterTest.cpp (diff) | clang.src/unittests/AST/ASTImporterTest.cpp |
Revision
364770
by kparzysz:
[Hexagon] Rework VLCR algorithm Add code to catch pattern for commutative instructions for VLCR. Patch by Suyog Sarda. |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /llvm/trunk/lib/Target/Hexagon/HexagonVectorLoopCarriedReuse.cpp (diff) | llvm.src/lib/Target/Hexagon/HexagonVectorLoopCarriedReuse.cpp |
| /llvm/trunk/test/CodeGen/Hexagon/hexagon_vector_loop_carried_reuse_commutative.ll | llvm.src/test/CodeGen/Hexagon/hexagon_vector_loop_carried_reuse_commutative.ll |
Revision
364769
by arsenm:
AMDGPU: Convert some places to Register |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /llvm/trunk/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.h (diff) | llvm.src/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.h |
| /llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.h (diff) | llvm.src/lib/Target/AMDGPU/SIMachineFunctionInfo.h |
Revision
364768
by arsenm:
AMDGPU/GlobalISel: Fix RegBankSelect for G_FCANONICALIZE |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp (diff) | llvm.src/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp |
| /llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcanonicalize.mir | llvm.src/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcanonicalize.mir |
Revision
364767
by arsenm:
AMDGPU/GlobalISel: Fix RegBankSelect for G_BUILD_VECTOR |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp (diff) | llvm.src/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp |
| /llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-build-vector.mir | llvm.src/test/CodeGen/AMDGPU/GlobalISel/regbankselect-build-vector.mir |
Revision
364766
by arsenm:
AMDGPU/GlobalISel: Fail on store to 32-bit address space |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp (diff) | llvm.src/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp |
| /llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-implicit-def.mir (diff) | llvm.src/test/CodeGen/AMDGPU/GlobalISel/inst-select-implicit-def.mir |
Revision
364765
by arsenm:
AMDGPU/GlobalISel: Improve icmp selection coverage. Select s64 eq/ne scalar icmp. |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp (diff) | llvm.src/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp |
| /llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.h (diff) | llvm.src/lib/Target/AMDGPU/AMDGPUInstructionSelector.h |
| /llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.s64.mir | llvm.src/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.s64.mir |
Revision
364764
by lebedevri:
[NFC][InstCombine] Improve test coverage for ((~x) + y) + 1 -> y - x fold fold (PR42459) So we indeed to have this fold, but only if +1 is not the last operation.. |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /llvm/trunk/test/Transforms/InstCombine/fold-inc-of-add-of-not-x-and-y-to-sub-x-from-y.ll (diff) | llvm.src/test/Transforms/InstCombine/fold-inc-of-add-of-not-x-and-y-to-sub-x-from-y.ll |
Revision
364763
by arsenm:
AMDGPU/GlobalISel: RegBankSelect for WWM/WQM |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp (diff) | llvm.src/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp |
| /llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.mir | llvm.src/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.mir |
| /llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wwm.mir | llvm.src/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wwm.mir |
Revision
364762
by arsenm:
AMDGPU/GlobalISel: Use vcc reg bank for amdgcn.wqm.vote |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp (diff) | llvm.src/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp |
 | /llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-wqm-vote.mir | llvm.src/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-wqm-vote.mir |
| /llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.vote.mir | llvm.src/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.vote.mir |
Revision
364761
by arsenm:
AMDGPU/GlobalISel: Fix scc->vcc copy handling This was checking the size of the register with the value of the size, which happens to be exec. Also fix assuming VCC is 64-bit to fix wave32. Also remove some untested handling for physical registers which is skipped. This doesn't insert the V_CNDMASK_B32 if SCC is the physical copy source. I'm not sure if this should be trying to handle this special case instead of dealing with this in copyPhysReg. |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp (diff) | llvm.src/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp |
| /llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp (diff) | llvm.src/lib/Target/AMDGPU/SIRegisterInfo.cpp |
| /llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir (diff) | llvm.src/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir |
Revision
364760
by arsenm:
AMDGPU/GlobalISel: Use and instead of BFE with inline immediate Zext from s1 is the only case where this should do anything with the current legal extensions. |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp (diff) | llvm.src/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp |
| /llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-anyext.mir (diff) | llvm.src/test/CodeGen/AMDGPU/GlobalISel/inst-select-anyext.mir |
| /llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir (diff) | llvm.src/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir |
| /llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir (diff) | llvm.src/test/CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir |
Revision
364759
by arsenm:
GlobalISel: Add GINodeEquiv for min/max |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /llvm/trunk/include/llvm/Target/GlobalISel/SelectionDAGCompat.td (diff) | llvm.src/include/llvm/Target/GlobalISel/SelectionDAGCompat.td |
| /llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-smax.mir | llvm.src/test/CodeGen/AMDGPU/GlobalISel/inst-select-smax.mir |
| /llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-smin.mir | llvm.src/test/CodeGen/AMDGPU/GlobalISel/inst-select-smin.mir |
| /llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-umax.mir | llvm.src/test/CodeGen/AMDGPU/GlobalISel/inst-select-umax.mir |
| /llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-umin.mir | llvm.src/test/CodeGen/AMDGPU/GlobalISel/inst-select-umin.mir |
Revision
364758
by arsenm:
GlobalISel: Add DAG compat for G_FCANONICALIZE |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /llvm/trunk/include/llvm/Target/GlobalISel/SelectionDAGCompat.td (diff) | llvm.src/include/llvm/Target/GlobalISel/SelectionDAGCompat.td |
| /llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcanonicalize.mir | llvm.src/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcanonicalize.mir |
Revision
364757
by atanasyan:
[mips] Add missing schedinfo for MSA and ASE instructions |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /llvm/trunk/lib/Target/Mips/MipsDSPInstrInfo.td (diff) | llvm.src/lib/Target/Mips/MipsDSPInstrInfo.td |
| /llvm/trunk/lib/Target/Mips/MipsMSAInstrInfo.td (diff) | llvm.src/lib/Target/Mips/MipsMSAInstrInfo.td |
| /llvm/trunk/lib/Target/Mips/MipsScheduleP5600.td (diff) | llvm.src/lib/Target/Mips/MipsScheduleP5600.td |
Revision
364756
by atanasyan:
[mips] Add missing schedinfo for atomic instructions |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (diff) | llvm.src/lib/Target/Mips/MipsInstrInfo.td |
| /llvm/trunk/lib/Target/Mips/MipsScheduleP5600.td (diff) | llvm.src/lib/Target/Mips/MipsScheduleP5600.td |
Revision
364755
by atanasyan:
[mips] Add missing schedinfo for ADJCALLSTACKDOWN, ADJCALLSTACKUP |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (diff) | llvm.src/lib/Target/Mips/MipsInstrInfo.td |
Revision
364752
by martong:
[ASTImporter] Propagate error from ImportDeclContext Summary: During analysis of one project we failed to import one CXXDestructorDecl. But since we did not propagate the error in importDeclContext we had a CXXRecordDecl without a destructor. Then the analyzer engine had a CallEvent where the nonexistent dtor was requested (crash). Solution is to propagate the errors we have during importing a DeclContext. Reviewers: a_sidorin, a.sidorin, shafik Subscribers: rnkovacs, dkrupp, Szelethus, gamesh411, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D63603 |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /cfe/trunk/lib/AST/ASTImporter.cpp (diff) | clang.src/lib/AST/ASTImporter.cpp |
| /cfe/trunk/unittests/AST/ASTImporterTest.cpp (diff) | clang.src/unittests/AST/ASTImporterTest.cpp |
Revision
364750
by fhahn:
[AMDGPU] Call isLoopExiting for blocks in the loop. isLoopExiting should only be called for blocks in the loop. A follow up patch makes this requirement an assertion. I've updated the usage here, to only match for actual exit blocks. Previously, it would also match blocks not in the loop. Reviewers: arsenm, nhaehnle Reviewed By: nhaehnle Differential Revision: https://reviews.llvm.org/D63980 |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp (diff) | llvm.src/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp |
Revision
364749
by lebedevri:
[NFC][InstCombine] Tests for ((~x) + y) + 1 -> y - x fold fold (PR42459) To be noted, this pattern is not unhandled by instcombine per-se, it is somehow does end up being folded when one runs opt -O3, but not if it's just -instcombine. Regardless, that fold is indirect, depends on some other folds, and is thus blind when there are extra uses. https://bugs.llvm.org/show_bug.cgi?id=42459 https://rise4fun.com/Alive/EPO0 |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /llvm/trunk/test/Transforms/InstCombine/fold-inc-of-add-of-not-x-and-y-to-sub-x-from-y.ll | llvm.src/test/Transforms/InstCombine/fold-inc-of-add-of-not-x-and-y-to-sub-x-from-y.ll |
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