FailedChanges

Summary

  1. AMDGPU: Correct properties for adjcallstack* pseudos These should be SALU writes, and these are lowered to instructions that def SCC.
  2. Fix broken C++ mode comment
  3. [InstCombine][NFCI] Update test cases in onehot_merge.ll Use both one bit and signbit shifting to check for one bit merge. Reviewers: lebedev.ri, spatel, efriedma, craig.topper Reviewed By: lebedev.ri Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D63903
  4. [InstCombine] reduce more checks for power-of-2-or-zero using ctpop Extends the transform from: rL364341 ...to include another (more common?) pattern that tests whether a value is a power-of-2 (including or excluding zero).
  5. Fix breakage introduced by D60974 D60974 added tests which incorrectly assume that llvm-readelf is available. This is a bad assumption, it should instead declare the dependency explicitly in the tests.
  6. [X86] Use v4i32 vzloads instead of v2i64 for vpmovzx/vpmovsx patterns where only 32-bits are loaded. v2i64 vzload defines a 64-bit memory access. It doesn't look like we have any coverage for this either way. Also remove some vzload usages where the instruction loads only 16-bits.
  7. [mips] Add missing schedinfo for MIPSeh_return[32|64] instructions
  8. [mips] Add virtualization ASE to P5600 scheduling definitions
  9. [mips] Add missing schedinfo for LONG_BRANCH_* instructions
  10. [X86] Remove several bad load folding isel patterns for VPMOVZX/VPMOVSX. These patterns all matched a v2i64 vzload which only loads 64-bits to instructions that load a full 128-bits.
  11. Revert [SLP] Look-ahead operand reordering heuristic. This reverts r364478 (git commit 574cb0eb3a7ac95e62d223a60bef891171dfe321) The patch is causing compilation timeouts.
  12. [NFC][InstCombine] More commutative tests for "shift direction in bittest" (PR42466) 'and' is commutative, if we don't want to touch shift-of-const, we still need to check the other hand of 'and'.
Revision 364859 by arsenm:
AMDGPU: Correct properties for adjcallstack* pseudos

These should be SALU writes, and these are lowered to instructions
that def SCC.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AMDGPU/SIInstructions.td (diff)llvm.src/lib/Target/AMDGPU/SIInstructions.td
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir (diff)llvm.src/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir (diff)llvm.src/test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/virtregrewrite-undef-identity-copy.mir (diff)llvm.src/test/CodeGen/AMDGPU/virtregrewrite-undef-identity-copy.mir
Revision 364858 by arsenm:
Fix broken C++ mode comment
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/IR/DiagnosticHandler.h (diff)llvm.src/include/llvm/IR/DiagnosticHandler.h
Revision 364857 by huihuiz:
[InstCombine][NFCI] Update test cases in onehot_merge.ll

Use both one bit and signbit shifting to check for one bit merge.

Reviewers: lebedev.ri, spatel, efriedma, craig.topper

Reviewed By: lebedev.ri

Subscribers: llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63903
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/Transforms/InstCombine/onehot_merge.ll (diff)llvm.src/test/Transforms/InstCombine/onehot_merge.ll
Revision 364856 by spatel:
[InstCombine] reduce more checks for power-of-2-or-zero using ctpop

Extends the transform from:
rL364341
...to include another (more common?) pattern that tests whether a
value is a power-of-2 (including or excluding zero).
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp (diff)llvm.src/lib/Transforms/InstCombine/InstCombineCompares.cpp
The file was modified/llvm/trunk/test/Transforms/InstCombine/ispow2.ll (diff)llvm.src/test/Transforms/InstCombine/ispow2.ll
Revision 364855 by jfb:
Fix breakage introduced by D60974

D60974 added tests which incorrectly assume that llvm-readelf is available. This is a bad assumption, it should instead declare the dependency explicitly in the tests.
Change TypePath in RepositoryPath in Workspace
The file was modified/cfe/trunk/test/CMakeLists.txt (diff)clang.src/test/CMakeLists.txt
Revision 364851 by ctopper:
[X86] Use v4i32 vzloads instead of v2i64 for vpmovzx/vpmovsx patterns where only 32-bits are loaded.

v2i64 vzload defines a 64-bit memory access. It doesn't look like
we have any coverage for this either way.

Also remove some vzload usages where the instruction loads only
16-bits.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86InstrAVX512.td (diff)llvm.src/lib/Target/X86/X86InstrAVX512.td
The file was modified/llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td (diff)llvm.src/lib/Target/X86/X86InstrFragmentsSIMD.td
The file was modified/llvm/trunk/lib/Target/X86/X86InstrSSE.td (diff)llvm.src/lib/Target/X86/X86InstrSSE.td
Revision 364850 by atanasyan:
[mips] Add missing schedinfo for MIPSeh_return[32|64] instructions
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (diff)llvm.src/lib/Target/Mips/MipsInstrInfo.td
Revision 364849 by atanasyan:
[mips] Add virtualization ASE to P5600 scheduling definitions
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/Mips/MipsScheduleP5600.td (diff)llvm.src/lib/Target/Mips/MipsScheduleP5600.td
Revision 364848 by atanasyan:
[mips] Add missing schedinfo for LONG_BRANCH_* instructions
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td (diff)llvm.src/lib/Target/Mips/Mips64InstrInfo.td
The file was modified/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (diff)llvm.src/lib/Target/Mips/MipsInstrInfo.td
Revision 364847 by ctopper:
[X86] Remove several bad load folding isel patterns for VPMOVZX/VPMOVSX.

These patterns all matched a v2i64 vzload which only loads 64-bits
to instructions that load a full 128-bits.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86InstrAVX512.td (diff)llvm.src/lib/Target/X86/X86InstrAVX512.td
The file was modified/llvm/trunk/lib/Target/X86/X86InstrSSE.td (diff)llvm.src/lib/Target/X86/X86InstrSSE.td
Revision 364846 by rupprecht:
Revert [SLP] Look-ahead operand reordering heuristic.

This reverts r364478 (git commit 574cb0eb3a7ac95e62d223a60bef891171dfe321)

The patch is causing compilation timeouts.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Transforms/Vectorize/SLPVectorizer.cpp (diff)llvm.src/lib/Transforms/Vectorize/SLPVectorizer.cpp
The file was modified/llvm/trunk/test/Transforms/SLPVectorizer/X86/lookahead.ll (diff)llvm.src/test/Transforms/SLPVectorizer/X86/lookahead.ll
Revision 364844 by lebedevri:
[NFC][InstCombine] More commutative tests for "shift direction in bittest" (PR42466)

'and' is commutative, if we don't want to touch shift-of-const,
we still need to check the other hand of 'and'.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/Transforms/InstCombine/shift-direction-in-bit-test.ll (diff)llvm.src/test/Transforms/InstCombine/shift-direction-in-bit-test.ll