Started 6 hr 53 min ago
Took 5 hr 45 min

Success Build #948 (Jan 22, 2020 6:44:07 AM)

Changes
  1. [mlir][spirv] Add lowering for composite std.constant. (detail)
  2. Extend misc-misplaced-const to detect using declarations as well as (detail)
  3. [llvm-mca][NFC] Regenerate tests @HEAD. (detail)
  4. Use SelectionDAG::getShiftAmountConstant(). NFCI. (detail)
  5. [SelectionDAG] getShiftAmountConstant - assert the type is an integer. (detail)
  6. [InstCombine] add tests for fneg+fadd; NFC (detail)
  7. AMDGPU: Fix missing immarg on llvm.amdgcn.interp.mov (detail)
  8. AMDGPU/GlobalISel: RegBankSelect interp intrinsics (detail)
  9. Revert "Extend misc-misplaced-const to detect using declarations as well (detail)
  10. [ASTImporter] Properly delete decls from SavedImportPaths (detail)
  11. AMDGPU: Fix interaction of tfe and d16 (detail)
  12. AMDGPU/GlobalISel: Handle atomic_inc/atomic_dec (detail)
  13. AMDGPU/GlobalISel: Fix RegbankSelect for llvm.amdgcn.fmul.legacy (detail)
  14. [MachineScheduler] Allow clustering mem ops with complex addresses (detail)
  15. [AArch64][SVE] Add patterns for unpredicated load/store to (detail)
  16. [ARM] MVE Gather Scatter cost model tests. NFC (detail)
  17. [ARM] Basic gather scatter cost model (detail)
  18. [VE] setcc isel patterns (detail)
  19. [InstCombine] fneg(X + C) --> -C - X (detail)
  20. Unconditionally enable lvalue function designators; NFC (detail)
  21. AMDGPU/GlobalISel: Add pre-legalize combiner pass (detail)
  22. AMDGPU: Do binop of select of constant fold in AMDGPUCodeGenPrepare (detail)
  23. AMDGPU: Look through casted selects to constant fold bin ops (detail)
  24. AMDGPU: Fix typo (detail)
  25. [VE] select and selectcc patterns (detail)
  26. [lldb/Target] Sort CMakeLists (NFC) (detail)
  27. AMDGPU/GlobalISel: Fold constant offset vector extract indexes (detail)
  28. [mlir] Swap use of to_vector() with lookupValues() in LLVMIRIntrinsicGen (detail)
  29. AMDGPU/GlobalISel: Fix RegBankSelect for G_INSERT_VECTOR_ELT (detail)
  30. AMDGPU/GlobalISel: Select G_INSERT_VECTOR_ELT (detail)
  31. [compiler-rt] [builtins] Fix clear_cache_test to work with MPROTECT (detail)
  32. [gn build] (manually) port a174f0da62f (detail)
  33. AMDGPU/GlobalISel: Fold add of constant into G_INSERT_VECTOR_ELT (detail)
  34. [X86][SSE] combineExtractWithShuffle - (detail)
  35. [RISCV] Support ABI checking with per function target-features (detail)
  36. AMDGPU/GlobalISel: Keep G_BITCAST out of waterfall loop (detail)
  37. AMDGPU: Fix element size assertion (detail)
  38. [AArch64] Add test for DWARF return address signing (detail)
  39. [PGO][PGSO] Update BFI in CodeGenPrepare::optimizeSelectInst. (detail)
  40. AMDGPU/GlobalISel: Select llvm.amdgcn.mov.dpp8 (detail)
  41. AMDGPU/GlobalISel: Select llvm.amdgcn.mov.dpp (detail)
  42. Regenerate test/CodeGen/ARM/vext.ll. NFC. (detail)
  43. Precommit NFC part of DAGCombiner change. NFC. (detail)
  44. [NFC][XCOFF] Refactor Csect creation into TargetLoweringObjectFile (detail)
  45. AMDGPU/GlobalISel: Handle 16-bank LDS llvm.amdgcn.interp.p1.f16 (detail)
  46. [AArch64] Don't rename registers with pseudo defs in Ld/St opt. (detail)
  47. [gn build] [win] produce symbolized stack frames in release builds too (detail)
  48. Revert "Unconditionally enable lvalue function designators; NFC" (detail)
  49. [scudo][standalone] Reduce Android region sizes to 128MB (detail)
  50. [Flang] add some cmake code to allow for out-of-tree building of MLIR (detail)
  51. Revert "[gn build] [win] produce symbolized stack frames in release (detail)
  52. Revert "[DA][TTI][AMDGPU] Add option to select GPUDA with TTI" (detail)
  53. [ARM] Mark MVE loads/store as not having side effects (detail)
  54. [X86][SSE] combineExtractWithShuffle - extract(bitcast(broadcast(x))) (detail)
  55. [CMake][Fuchsia] Disable in-process cc1 (detail)
  56. Add a comment about when we can remove this construct; NFC. (detail)
  57. [Concepts] Fix bug when referencing function parameters in instantiated (detail)

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This run spent:

  • 7 hr 57 min waiting;
  • 5 hr 45 min build duration;
  • 9 hr 36 min total from scheduled to completion.
Revision: f54354cb3888376b0ce8b536d46c5a5a47d5394f
  • refs/remotes/origin/master
Revision: c2a250e1c43c05925fe040dc9624403af7879453
  • refs/remotes/origin/master
Revision: f54354cb3888376b0ce8b536d46c5a5a47d5394f
  • refs/remotes/origin/master
Test Result (no failures)
    Revision: 6a075b6de4cafebec9ca1ff9eec7229a617c93f6
    • llvmorg-5.0.2
    Revision: d0d8eb2e5415b8be29343e3c17a18e49e67b5551
    • llvmorg-7.0.1
    Revision: 0399d5a9682b3cef71c653373e38890c63c4c365
    • llvmorg-9.0.0