SuccessChanges

Summary

  1. [Scheduler] Adjust interface of CreateTargetMIHazardRecognizer to use (details)
  2. [Attributor] AAValueConstantRange: Value range analysis using constant (details)
  3. [ARM] Reegenerate MVE tests. NFC (details)
  4. [X86] Don't call LowerUINT_TO_FP_i32 for i32->f80 on 32-bit targets with (details)
  5. [VE] Minimal codegen for empty functions (details)
  6. [AMDGPU] Invert the handling of skip insertion. (details)
  7. [MachO] Add a test for detecting reserved unit length. (details)
  8. [gn build] Port 0dc6c249bff (details)
  9. [DWARF] Fix DWARFDebugAranges to support 64-bit CU offsets. (details)
Commit b891490ceb390b9c9ccc93abf08c2c1bec50e340 by david.green
[Scheduler] Adjust interface of CreateTargetMIHazardRecognizer to use
ScheduleDAGMI. NFC
All the callers of this function will be ScheduleDAGMI from the
MachineScheduler. This allows us to use the extra info available in
ScheduleDAGMI without resorting to awkward casts.
The file was modifiedllvm/include/llvm/CodeGen/TargetInstrInfo.h (diff)
The file was modifiedllvm/lib/CodeGen/TargetInstrInfo.cpp (diff)
Commit 188f9a348dc545bf9a420d998ad37761bddd7285 by uenoku.tokotoko
[Attributor] AAValueConstantRange: Value range analysis using constant
range
Summary: This patch introduces `AAValueConstantRange`, which answers a
possible range for integer value in a specific program point. One of the
motivations is propagating existing `range` metadata. (I think we need
to change the situation that `range` metadata cannot be put to
Argument).
The state is a tuple of `ConstantRange` and it is initialized to (known,
assumed) = ([-∞, +∞], empty).
Currently, AAValueConstantRange is created in `getAssumedConstant`
method when `AAValueSimplify` returns `nullptr`(worst state).
Supported
- BinaryOperator(add, sub, ...)
- CmpInst(icmp eq, ...)
- !range metadata
`AAValueConstantRange` is not intended to extend to polyhedral range
value analysis.
Reviewers: jdoerfert, sstefan1
Reviewed By: jdoerfert
Subscribers: phosek, davezarzycki, baziotis, hiraditya, javed.absar,
llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D71620
The file was modifiedllvm/test/Transforms/Attributor/IPConstantProp/solve-after-each-resolving-undefs-for-function.ll (diff)
The file was modifiedllvm/lib/Transforms/IPO/Attributor.cpp (diff)
The file was addedllvm/test/Transforms/Attributor/lvi-for-ashr.ll
The file was addedllvm/test/Transforms/Attributor/lvi-after-jumpthreading.ll
The file was modifiedllvm/test/Transforms/Attributor/dereferenceable-1.ll (diff)
The file was addedllvm/test/Transforms/Attributor/range.ll
The file was modifiedllvm/test/Transforms/Attributor/IPConstantProp/return-constant.ll (diff)
The file was modifiedllvm/include/llvm/Transforms/IPO/Attributor.h (diff)
The file was modifiedllvm/test/Transforms/Attributor/value-simplify.ll (diff)
Commit 1b264a8263f8656bd9c09c471af9b43422429ef6 by david.green
[ARM] Reegenerate MVE tests. NFC
The mve-phireg.ll test no longer really tests what it was added for, but
the original case was fairly complex. I've left the test in as a general
codegen test.
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vpt-block-fold-vcmp.mir (diff)
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-1-pred.mir (diff)
The file was modifiedllvm/test/CodeGen/Thumb2/mve-phireg.ll (diff)
The file was modifiedllvm/test/CodeGen/Thumb2/mve-stacksplot.mir (diff)
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-non-consecutive-ins.mir (diff)
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vpt-block-optnone.mir (diff)
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vpt-from-intrinsics.ll (diff)
Commit be8f217b180e134d568ff491b045d05c137b6234 by craig.topper
[X86] Don't call LowerUINT_TO_FP_i32 for i32->f80 on 32-bit targets with
sse2.
We were performing an emulated i32->f64 in the SSE registers, then
storing that value to memory and doing a extload into the X87 domain.
After this patch we'll now just store the i32 to memory along with an
i32 0. Then do a 64-bit FILD to f80 completely in the X87 unit. This
matches what we do without SSE.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp (diff)
The file was modifiedllvm/test/CodeGen/X86/scalar-int-to-fp.ll (diff)
Commit 064859bde79ccd221fd5196fd2d889014c5435c4 by simon.moll
[VE] Minimal codegen for empty functions
Summary: This patch implements minimal VE code generation for empty
function bodies (no args, no value return).
Contents
* empty function code generation test.
* Minimal function prologue & epilogue emission
* Instruction formats and instruction definitions as far as required for
the empty function prologue & epilogue.
* I64 register class definitions.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D72598
The file was addedllvm/lib/Target/VE/VEInstrInfo.cpp
The file was modifiedllvm/lib/Target/VE/MCTargetDesc/VEMCTargetDesc.cpp (diff)
The file was modifiedllvm/lib/Target/VE/VE.h (diff)
The file was addedllvm/lib/Target/VE/VESubtarget.cpp
The file was addedllvm/lib/Target/VE/VERegisterInfo.h
The file was addedllvm/lib/Target/VE/VERegisterInfo.cpp
The file was addedllvm/lib/Target/VE/InstPrinter/LLVMBuild.txt
The file was addedllvm/lib/Target/VE/MCTargetDesc/VEMCAsmInfo.h
The file was modifiedllvm/lib/Target/VE/MCTargetDesc/LLVMBuild.txt (diff)
The file was addedllvm/lib/Target/VE/VEFrameLowering.h
The file was addedllvm/lib/Target/VE/VERegisterInfo.td
The file was addedllvm/lib/Target/VE/VEInstrInfo.td
The file was addedllvm/lib/Target/VE/MCTargetDesc/VETargetStreamer.cpp
The file was modifiedllvm/lib/Target/VE/LLVMBuild.txt (diff)
The file was modifiedllvm/lib/Target/VE/MCTargetDesc/VEMCTargetDesc.h (diff)
The file was addedllvm/lib/Target/VE/VEAsmPrinter.cpp
The file was addedllvm/lib/Target/VE/VEInstrFormats.td
The file was addedllvm/lib/Target/VE/VEMCInstLower.cpp
The file was addedllvm/lib/Target/VE/VEISelLowering.h
The file was addedllvm/lib/Target/VE/VEInstrInfo.h
The file was addedllvm/lib/Target/VE/MCTargetDesc/VETargetStreamer.h
The file was addedllvm/test/CodeGen/VE/simple_prologue_epilogue.ll
The file was addedllvm/lib/Target/VE/VEFrameLowering.cpp
The file was addedllvm/lib/Target/VE/VEISelLowering.cpp
The file was addedllvm/lib/Target/VE/VETargetTransformInfo.h
The file was addedllvm/lib/Target/VE/VE.td
The file was modifiedllvm/lib/Target/VE/CMakeLists.txt (diff)
The file was addedllvm/lib/Target/VE/InstPrinter/CMakeLists.txt
The file was addedllvm/lib/Target/VE/VESubtarget.h
The file was addedllvm/lib/Target/VE/InstPrinter/VEInstPrinter.h
The file was addedllvm/lib/Target/VE/VEISelDAGToDAG.cpp
The file was modifiedllvm/lib/Target/VE/MCTargetDesc/CMakeLists.txt (diff)
The file was addedllvm/lib/Target/VE/InstPrinter/VEInstPrinter.cpp
The file was modifiedllvm/lib/Target/VE/VETargetMachine.cpp (diff)
The file was modifiedllvm/lib/Target/VE/VETargetMachine.h (diff)
The file was addedllvm/lib/Target/VE/MCTargetDesc/VEMCAsmInfo.cpp
The file was addedllvm/lib/Target/VE/VECallingConv.td
Commit 0dc6c249bffac9f23a605ce4e42a84341da3ddbd by cdevadas
[AMDGPU] Invert the handling of skip insertion.
The current implementation of skip insertion (SIInsertSkip) makes it a
mandatory pass required for correctness. Initially, the idea was to have
an optional pass. This patch inserts the s_cbranch_execz upfront during
SILowerControlFlow to skip over the sections of code when no lanes are
active. Later, SIRemoveShortExecBranches removes the skips for short
branches, unless there is a sideeffect and the skip branch is really
necessary.
This new pass will replace the handling of skip insertion in the
existing SIInsertSkip Pass.
Differential revision: https://reviews.llvm.org/D68092
The file was modifiedllvm/test/CodeGen/AMDGPU/collapse-endcf.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/ret_jump.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/uniform-cfg.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/valu-i1.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/insert-skips-kill-uncond.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/smrd_vmem_war.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/uniform-loop-inside-nonuniform.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/cse-phi-incoming-val.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/insert-skips-ignored-insts.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/wave32.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/si-lower-control-flow.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/skip-if-dead.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/wqm.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/atomic_optimizations_pixelshader.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/hoist-cond.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/else.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/si-lower-control-flow-unreachable-block.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll (diff)
The file was modifiedllvm/lib/Target/AMDGPU/SIInsertSkips.cpp (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/insert-skips-gws.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/si-annotate-cf-noloop.ll (diff)
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp (diff)
The file was modifiedllvm/lib/Target/AMDGPU/SILowerControlFlow.cpp (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/branch-relaxation.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/skip-branch-taildup-ret.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/insert-skips-flat-vmem.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/call-skip.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/skip-branch-trap.ll (diff)
The file was addedllvm/lib/Target/AMDGPU/SIRemoveShortExecBranches.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/convergent-inlineasm.ll (diff)
The file was modifiedllvm/lib/Target/AMDGPU/CMakeLists.txt (diff)
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPU.h (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/branch-condition-and.ll (diff)
Commit fcc08aa835de1e0c1f3e7e479917575e55433b68 by ikudrin
[MachO] Add a test for detecting reserved unit length.
This is a follow-up for D71546 to add a corresponding unit test.
Differential Revision: https://reviews.llvm.org/D72695
The file was modifiedlld/unittests/MachOTests/MachONormalizedFileToAtomsTests.cpp (diff)
Commit 4b1d471fa61f2d390d4dd5f2e95862a3cb5a6ec0 by llvmgnsyncbot
[gn build] Port 0dc6c249bff
The file was modifiedllvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn (diff)
Commit 2142e20f50954b9b5085e9b9461efc318a3348c0 by ikudrin
[DWARF] Fix DWARFDebugAranges to support 64-bit CU offsets.
DWARFContext, the only user of this class, can already handle such
offsets.
Differential Revision: https://reviews.llvm.org/D71834
The file was modifiedllvm/lib/DebugInfo/DWARF/DWARFDebugAranges.cpp (diff)
The file was modifiedllvm/include/llvm/DebugInfo/DWARF/DWARFDebugAranges.h (diff)