FailedChanges

Summary

  1. Use a fast path when initializing LineOffsetMapping (details)
  2. [DAG] visitVECTOR_SHUFFLE - move shuffle canonicalization/merges all under the same legality test. NFCI. (details)
  3. [libc++] [docs] [C++2b] Update status page with issues (and forgotten papers) adopted in November 2020 and February 2021 virtual meetings. (details)
  4. [Driver] Don't litter the source directory in test (details)
  5. [lldb/Interpreter] Pacify -Wnon-virtual-dtor (details)
  6. [Statepoint Lowering] Consider dead deopt gc values together with other gc values (details)
  7. [CodeGen] Fix issues with subvector intrinsic index types (details)
  8. Revert "[flang] Detect circularly defined interfaces of procedures" (details)
  9. [DAG] visitVECTOR_SHUFFLE - attempt to match commuted shuffles with MergeInnerShuffle. (details)
  10. [LV] Generate RT checks up-front and remove them if required. (details)
  11. [SEH] capture 'this' (details)
  12. [RISCV] Support EXTRACT_SUBVECTOR on vector masks (details)
  13. [RISCV] Unify scalable- and fixed-vector INSERT_SUBVECTOR lowering (details)
Commit 80e8efd563fda4d7b125b834d3243b3ef9a05270 by sguelton
Use a fast path when initializing LineOffsetMapping

Use the fact that the number of line break is lower than printable characters to
guide the optimization process. Also use a fuzzy test that catches both \n and
\r in a single check to speedup the computation.

Differential Revision: https://reviews.llvm.org/D97320
The file was modifiedclang/lib/Basic/SourceManager.cpp
Commit 64c41301ce4c3bfc1f5d42423595b9084e36a824 by llvm-dev
[DAG] visitVECTOR_SHUFFLE - move shuffle canonicalization/merges all under the same legality test. NFCI.

Minor cleanup to move related combines closer together to make it more coherent, without changing the ordering.
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Commit 11ef785cdd0299a719632ef8fbc34f54f3db0674 by marek.kurdej
[libc++] [docs] [C++2b] Update status page with issues (and forgotten papers) adopted in November 2020 and February 2021 virtual meetings.

Sources:
* https://github.com/cplusplus/draft/pull/4380 (November 2020)
* https://github.com/cplusplus/draft/pull/4523 (February 2021)
* https://github.com/cplusplus/draft/issues?q=is%3Aissue+LWG+Motion
The file was modifiedlibcxx/docs/Cxx2bStatusPaperStatus.csv
The file was modifiedlibcxx/docs/Cxx2bStatus.rst
The file was addedlibcxx/docs/Cxx2bStatusIssuesStatus.csv
Commit 965f24d4dbd6bc8905de75150d36c693d4396bfd by benny.kra
[Driver] Don't litter the source directory in test
The file was modifiedclang/test/Driver/cc-print-proc-stat.c
Commit 99c24f7aa8ccb84abde1672255439a2b2730ccc1 by benny.kra
[lldb/Interpreter] Pacify -Wnon-virtual-dtor
The file was modifiedlldb/unittests/Interpreter/TestOptionValue.cpp
Commit 65fb706231df51b18d3a76bc083395c08924e991 by serguei.katkov
[Statepoint Lowering] Consider dead deopt gc values together with other gc values

Currently dead gc value mentioned in the deopt section are not listed in gc section
and so are processed separately.
With this CL all deopt gc values are considered as base pointers and processed in the
same way as other gc values.

The fact that deopt gc pointer is a base pointer was used all the time but
it is explicitly documented here by putting the value in SI.Base.

The idea of the patch comes from Philip Reames.

Reviewers: reames, dantrushin
Reviewed By: reames
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D97554
The file was modifiedllvm/test/CodeGen/X86/statepoint-vreg-details.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/StatepointLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/statepoint-vreg-invoke.ll
The file was modifiedllvm/test/CodeGen/X86/statepoint-vreg.ll
Commit 6718fda6ada87169f8ee4b8bebf13bf39b83533b by fraser
[CodeGen] Fix issues with subvector intrinsic index types

This patch addresses issues arising from the fact that the index type
used for subvector insertion/extraction is inconsistent between the
intrinsics and SDNodes. The intrinsic forms require i64 whereas the
SDNodes use the type returned by SelectionDAG::getVectorIdxTy.

Rather than update the intrinsic definitions to use an overloaded index
type, this patch fixes the issue by transforming the index to the
correct type as required. Any loss of index bits going from i64 to a
smaller type is unexpected, and will be caught by an assertion in
SelectionDAG::getVectorIdxConstant.

The patch also updates the documentation for INSERT_SUBVECTOR and adds
an assertion to its creation to bring it in line with EXTRACT_SUBVECTOR.
This necessitated changes to AArch64 which was using i64 for
EXTRACT_SUBVECTOR but i32 for INSERT_SUBVECTOR. Only one test changed
its codegen after updating the backend accordingly.

Reviewed By: sdesmalen

Differential Revision: https://reviews.llvm.org/D97459
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrFormats.td
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/RISCV/rvv/extract-subvector.ll
The file was modifiedllvm/test/CodeGen/AArch64/vecreduce-and-legalization.ll
The file was modifiedllvm/include/llvm/CodeGen/ISDOpcodes.h
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.td
Commit 00e6513374eb961065d6830b30205fb0f3001c43 by andrzej.warzynski
Revert "[flang] Detect circularly defined interfaces of procedures"

This reverts commit 07de0846a5055015b55dc2b8faa2143f9902e549.

The original patch has caused 6 out 8 of Flang's public buildbots to
fail. As I'm not sure what the fix should be, I'm reverting this for
now. Please see https://reviews.llvm.org/D97201 for more context and
discussion.
The file was modifiedflang/include/flang/Semantics/symbol.h
The file was modifiedflang/lib/Semantics/resolve-names.cpp
The file was modifiedflang/test/Semantics/resolve102.f90
The file was modifiedflang/lib/Evaluate/characteristics.cpp
Commit 9dd83f5ee8697fdb41ba73bc70d845085715b01d by llvm-dev
[DAG] visitVECTOR_SHUFFLE - attempt to match commuted shuffles with MergeInnerShuffle.

Try to match "shuffle(C, shuffle(A, B, M0), M1) -> shuffle(A, B, M2)" etc. by using MergeInnerShuffle's commuted inner shuffle mode.
The file was modifiedllvm/test/CodeGen/Thumb2/mve-shuffle.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vld3.ll
The file was modifiedllvm/test/CodeGen/X86/oddshuffles.ll
The file was modifiedllvm/test/CodeGen/X86/pr34592.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Commit 53dacb7b67758f0c5ea2fe6a3c2030d070017b42 by flo
[LV] Generate RT checks up-front and remove them if required.

This patch updates LV to generate the runtime checks just after cost
modeling, to allow a more precise estimate of the actual cost of the
checks. This information will be used in future patches to generate
larger runtime checks in cases where the checks only make up a small
fraction of the expected scalar loop execution time.

The runtime checks are created up-front in a temporary block to allow better
estimating the cost and un-linked from the existing IR. After deciding to
vectorize, the checks are moved backed. If deciding not to vectorize, the
temporary block is completely removed.

This patch is similar in spirit to D71053, but explores a different
direction: instead of delaying the decision on whether to vectorize in
the presence of runtime checks it instead optimistically creates the
runtime checks early and discards them later if decided to not
vectorize. This has the advantage that the cost-modeling decisions
can be kept together and can be done up-front and thus preserving the
general code structure. I think delaying (part) of the decision to
vectorize would also make the VPlan migration a bit harder.

One potential drawback of this patch is that we speculatively
generate IR which we might have to clean up later. However it seems like
the code required to do so is quite manageable.

Reviewed By: lebedev.ri, ebrevnov

Differential Revision: https://reviews.llvm.org/D75980
The file was modifiedllvm/include/llvm/Transforms/Utils/ScalarEvolutionExpander.h
The file was modifiedllvm/test/Transforms/LoopVectorize/pr47343-expander-lcssa-after-cfg-update.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/X86/illegal-parallel-loop-uniform-write.ll
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
The file was addedllvm/test/Transforms/LoopVectorize/runtime-drop-crash.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/skeleton-lcssa-crash.ll
The file was modifiedllvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
Commit 1b04bdc2f3ffaa7a0e1e3dbdc3a0cd08f0b9a4ce by ogoffart
[SEH] capture 'this'

Simply make sure that the CodeGenFunction::CXXThisValue and CXXABIThisValue
are correctly initialized to the recovered value.
For lambda capture, we also need to make sure to fill the LambdaCaptureFields

Differential Revision: https://reviews.llvm.org/D97534
The file was modifiedclang/test/CodeGenCXX/exceptions-seh-filter-captures.cpp
The file was modifiedclang/lib/CodeGen/CGException.cpp
Commit bd4d4216881d2ddba170808a8cd2f7b75cbc8de9 by fraser
[RISCV] Support EXTRACT_SUBVECTOR on vector masks

This patch adds support for extracting subvectors from vector masks.
This can be either extracting a scalable vector from another, or a fixed-length
vector from a fixed-length or scalable vector.

Since RVV lacks a way to slide vector masks down on an element-wise
basis and we don't know the true length of the vector registers, in many
cases we must resort to using equivalently-sized i8 vectors to perform
the operation. When this is not possible we fall back and extend to a
suitable i8 vector.

Support was also added for fixed-length truncation to mask types.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D97475
The file was modifiedllvm/test/CodeGen/RISCV/rvv/extract-subvector.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
Commit 4ea734e6ec9da0587da733424fe616b7e401cf8c by fraser
[RISCV] Unify scalable- and fixed-vector INSERT_SUBVECTOR lowering

This patch unifies the two disparate paths for lowering INSERT_SUBVECTOR
operations under one roof. Consequently, with this patch it is possible to
support any fixed-length subvector insertion, not just "cast-like" ones.

As before, support for the insertion of mask vectors will come in a
separate patch.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D97543
The file was modifiedllvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
The file was addedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll