SuccessChanges

Summary

  1. [NFC] Separate bitcode reading for FUNC_CODE_INST_CMPXCHG(_OLD) (details)
  2. Revert a test using padding bits in atomics (details)
  3. [gcov] Don't split entry block; add a synthetic entry block instead (details)
  4. [InstCombine] add tests for add/sub-of-shl; NFC (details)
  5. [Hexagon] Account for truncating pairs to non-pairs when widening truncates (details)
  6. [gcov] Give the __llvm_gcov_ctr load instruction a name for more readable output (details)
  7. [MC] Resolve the difference of symbols in consecutive MCDataFragements (details)
  8. [AMDGPU] Correct gfx1031 XNACK setting documentation (details)
  9. [X86] Add support for using fast short rep mov for memcpy lowering. (details)
  10. Wordsmith RegionBranchOpInterface verification errors (details)
  11. [libc][MPFRWrapper] Provide a way to include MPFR header in downstream repos. (details)
  12. [GlobalISel] Rewrite the elide-br-by-swapping-icmp-ops combine to do less. (details)
  13. [GlobalISel][IRTranslator] Generate better conditional branch lowering. (details)
  14. [X86] Add tests for minnum/maxnum with constant NaN (NFC) (details)
  15. [GlobalISel] Enable usage of BranchProbabilityInfo in IRTranslator. (details)
  16. Add REQUIRES: asserts to a test that uses an asserts only flag. (details)
  17. [lldb] Pass the arch as part of the triple in the ARCH_CFLAGS (details)
Commit 5a4a0cfcfb54be4a64129ff91d95229b4a7eec75 by gchatelet
[NFC] Separate bitcode reading for FUNC_CODE_INST_CMPXCHG(_OLD)

This is preparatory work to unable storing alignment for AtomicCmpXchgInst.
See D83136 for context and bug: https://bugs.llvm.org/show_bug.cgi?id=27168

This is the fixed version of D83375, which was submitted and reverted.

Differential Revision: https://reviews.llvm.org/D87373
The file was modifiedllvm/include/llvm/Bitcode/LLVMBitCodes.h
The file was modifiedllvm/lib/Bitcode/Reader/BitcodeReader.cpp
Commit 11352fa83bcb6dcff1f6704e6dcd1102bfc1aa53 by ogiroux
Revert a test using padding bits in atomics
The file was modifiedlibcxx/test/std/atomics/atomics.types.operations/atomics.types.operations.req/atomic_helpers.h
Commit dbac20bb6bfbf44dc25ce4c0e1a0ec422fa5cffb by i
[gcov] Don't split entry block; add a synthetic entry block instead

The entry block is split at the first instruction where `shouldKeepInEntry`
returns false. The created basic block has a br jumping to the original entry
block. The new basic block causes the function label line and the other entry
block lines to be covered by different basic blocks, which can affect line
counts with special control flows (fork/exec in the entry block requires
heuristics in llvm-cov gcov to get consistent line counts).

  int main() { // BB0
    return 0;  // BB2 (due to entry block splitting)
  }
  // BB1 is the exit block (since gcov 4.8)

This patch adds a synthetic entry block (like PGOInstrumentation and GCC) and
inserts an edge from the synthetic entry block to the original entry block. We
can thus remove the tricky `shouldKeepInEntry` and entry block splitting. The
number of basic blocks does not change, but the emitted .gcno files will be
smaller because we can save one GCOV_TAG_LINES tag.

  // BB0 is the synthetic entry block with a single edge to BB2
  int main() { // BB2
    return 0;  // BB2
  }
  // BB1 is the exit block (since gcov 4.8)
The file was modifiedllvm/lib/Transforms/Instrumentation/GCOVProfiling.cpp
The file was modifiedllvm/test/Transforms/GCOVProfiling/atomic-counter.ll
Commit 1dd4c4e0a8e21ebb221a2b18f7cc774b2ac6259a by spatel
[InstCombine] add tests for add/sub-of-shl; NFC
The file was addedllvm/test/Transforms/InstCombine/shl-factor.ll
Commit 0ee54cf88329c50f25872ac1c67d7ae60ee3154c by kparzysz
[Hexagon] Account for truncating pairs to non-pairs when widening truncates

Added missing selection patterns for vpackl.
The file was addedllvm/test/CodeGen/Hexagon/autohvx/isel-widen-truncate-pair.ll
The file was modifiedllvm/lib/Target/Hexagon/HexagonPatternsHVX.td
Commit ad61e346d302eccbc12fdfb81ea1b0cd28e80010 by i
[gcov] Give the __llvm_gcov_ctr load instruction a name for more readable output
The file was modifiedllvm/lib/Transforms/Instrumentation/GCOVProfiling.cpp
Commit 415a4fbea7c1a39c780caa3cb7287fe09c5267d2 by caij2003
[MC] Resolve the difference of symbols in consecutive MCDataFragements

Try to resolve the difference of two symbols in consecutive MCDataFragments.
This is important for an idiom like "foo:instr; .if . - foo; instr; .endif"
(https://bugs.llvm.org/show_bug.cgi?id=43795).

Reviewed By: nickdesaulniers

Differential Revision: https://reviews.llvm.org/D69411
The file was addedllvm/test/MC/ARM/directive-if-subtraction.s
The file was modifiedllvm/lib/MC/MCExpr.cpp
The file was modifiedllvm/test/MC/MachO/reloc-diff.s
The file was modifiedllvm/include/llvm/MC/MCFragment.h
The file was modifiedllvm/lib/MC/MCSection.cpp
Commit 72e2fbde5456cfaa03f60750f7f421b165824cc8 by Tony.Tye
[AMDGPU] Correct gfx1031 XNACK setting documentation

- gfx1031 does not support XNACK.

Differential Revision: https://reviews.llvm.org/D87198
The file was modifiedllvm/docs/AMDGPUUsage.rst
Commit 0ab6a1569806783fcbf6303c462f051e9b5f764b by yamauchi
[X86] Add support for using fast short rep mov for memcpy lowering.

Disabled by default behind an option.

Differential Revision: https://reviews.llvm.org/D86883
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was addedllvm/test/CodeGen/X86/memcpy-inline-fsrm.ll
The file was modifiedllvm/lib/Target/X86/X86SelectionDAGInfo.cpp
Commit be35264ab5a38e8367dde49acfbfa1dd71230dfc by silvasean
Wordsmith RegionBranchOpInterface verification errors

I was having a lot of trouble parsing the messages. In particular, the
messages like:

```
<stdin>:3:8: error: 'scf.if' op  along control flow edge from Region #0 to scf.if source #1 type '!npcomprt.tensor' should match input #1 type 'tensor<?xindex>'
```

In particular, one thing that kept catching me was parsing the "to scf.if
source #1 type" as one thing, but really it is
"to parent results: source type #1".

Differential Revision: https://reviews.llvm.org/D87334
The file was modifiedmlir/test/Dialect/SCF/invalid.mlir
The file was modifiedmlir/lib/Interfaces/ControlFlowInterfaces.cpp
Commit fb542b0b8c209b05ba3100baf01718961e30fc26 by sivachandra
[libc][MPFRWrapper] Provide a way to include MPFR header in downstream repos.

Reviewed By: asteinhauser

Differential Revision: https://reviews.llvm.org/D87412
The file was modifiedlibc/utils/MPFRWrapper/MPFRUtils.cpp
Commit cc76da7adab71f0b6559ea13069f899b2ecbf70c by Amara Emerson
[GlobalISel] Rewrite the elide-br-by-swapping-icmp-ops combine to do less.

This combine previously tried to take sequences like:
  %cond = G_ICMP pred, a, b
  G_BRCOND %cond, %truebb
  G_BR %falsebb
%truebb:
  ...
%falsebb:
  ...

and by inverting the compare predicate and swapping branch targets, delete the
G_BR and instead have a single conditional branch to the falsebb. Since in an
earlier patch we have a combine to fold not(icmp) into just an inverted icmp,
we don't need this combine to do as much. This patch instead generalizes the
combine by just looking for:
  G_BRCOND %cond, %truebb
  G_BR %falsebb
%truebb:
  ...
%falsebb:
  ...

and then inverting the condition using a not (xor). The xor can be folded away
in a separate combine. This change also lets us avoid some optimization code
in the IRTranslator.

I also think that deleting G_BRs in the combiner is unnecessary. That's
something that targets can decide to do at selection time and could simplify
generic code in future.

Differential Revision: https://reviews.llvm.org/D86664
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.is.shared.ll
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/Utils.h
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-br.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUCombine.td
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.is.private.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
The file was modifiedllvm/include/llvm/Target/GlobalISel/Combine.td
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/select-constant.mir
The file was modifiedllvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
The file was modifiedllvm/lib/CodeGen/GlobalISel/Utils.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/bool-legalization.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64Combine.td
The file was removedllvm/test/CodeGen/AArch64/GlobalISel/const-0.ll
Commit 467a07128533276e3457b72a775e43190bdc1071 by Amara Emerson
[GlobalISel][IRTranslator] Generate better conditional branch lowering.

This is a port of the functionality from SelectionDAG, which tries to find
a tree of conditions from compares that are then combined using OR or AND,
before using that result as the input to a branch. Instead of naively
lowering the code as is, this change converts that into a sequence of
conditional branches on the sub-expressions of the tree.

Like SelectionDAG, we re-use the case block codegen functionality from
the switch lowering utils, which causes us to generate some different code.
The result of which I've tried to mitigate in earlier combine patches.

Differential Revision: https://reviews.llvm.org/D86665
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h
The file was modifiedllvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/long_ambiguous_chain_s64.ll
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/irtranslator-condbr-lower-tree.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/long_ambiguous_chain_s32.ll
Commit 91656fcb57ec6878833aba615e1142225514e13b by nikita.ppv
[X86] Add tests for minnum/maxnum with constant NaN (NFC)
The file was modifiedllvm/test/CodeGen/X86/fmaxnum.ll
The file was modifiedllvm/test/CodeGen/X86/fminnum.ll
Commit e5784ef8f6c6a7779f5dfc8f989ea37d233be388 by Amara Emerson
[GlobalISel] Enable usage of BranchProbabilityInfo in IRTranslator.

We weren't using this before, so none of the MachineFunction CFG edges had the
branch probability information added. As a result, block placement later in the
pipeline was flying blind.

This is enabled only with optimizations enabled like SelectionDAG.

Differential Revision: https://reviews.llvm.org/D86824
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/irtranslator-condbr-lower-tree.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
The file was modifiedllvm/lib/Target/X86/X86TargetMachine.cpp
The file was modifiedllvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVTargetMachine.cpp
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/irtranslator-switch-bittest.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64TargetMachine.cpp
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/swifterror.ll
The file was modifiedllvm/test/CodeGen/X86/GlobalISel/phi.ll
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h
The file was modifiedllvm/lib/Target/ARM/ARMTargetMachine.cpp
The file was modifiedllvm/lib/Target/Mips/MipsTargetMachine.cpp
Commit a9f79707624fe20e7ac19c5063d77190baa8b281 by Amara Emerson
Add REQUIRES: asserts to a test that uses an asserts only flag.
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-br.mir
Commit 2955a27abc25cd1b9d737c211c2cfe11e2a5de3e by Jonas Devlieghere
[lldb] Pass the arch as part of the triple in the ARCH_CFLAGS
The file was modifiedlldb/packages/Python/lldbsuite/test/builders/darwin.py