SuccessChanges

Summary

  1. Changed to use cmake arguments to specify C and C++ compilers. (details)
  2. Add ARM64 Windows on Arm buildbots (details)
  3. ang-x86-ninja removed MSVC environment setup (details)
  4. fixed compiler argument (details)
Commit 94e652786cb7bbf750d37816c4f099aa4081f4be by gkistanova
Changed to use cmake arguments to specify C and C++ compilers.
The file was modifiedzorg/buildbot/builders/ClangBuilder.py (diff)
Commit 2800bc5c7c1f9efc5e8733ef4d56963758ef24d7 by maxim.kuvyrkov
Add ARM64 Windows on Arm buildbots

This patch adds 2 new machines:
* linaro-armv8-windows-msvc-01
* linaro-armv8-windows-msvc-02
and 2 new builders:
* clang-arm64-windows-msvc
* clang-arm64-windows-msvc-2stage
to test LLVM on Windows on Arm platform.

The machines are Microsoft Surface X Pro laptops configured for 24x7 workload.

The host build environment is bootstrapped based on LLVM 11 custom build and
uses headers and libraries from MS Visual Studio 2019.  To accommodate the custom
setup we add "manual" value for "vs" parameter to ClangBuilder factory, which allows
to use manually pre-configured MSVC environment instead of initializing it during
build by running old-school vcvarsall.bat.

Finally, the bots have known failures in MCJIT unit-tests, which we are working on.
Once the failures are fixed, we'll enable unit-testsuite in both builders.

Reviewed By: gkistanova, omjavaid

Differential Revision: https://reviews.llvm.org/D87186
The file was modifiedzorg/buildbot/builders/ClangBuilder.py (diff)
The file was modifiedbuildbot/osuosl/master/config/builders.py (diff)
The file was modifiedbuildbot/osuosl/master/config/slaves.py (diff)
Commit 0e2cebb40db7ff0a5e10f02041f1c3a6c106b937 by kuhnel
ang-x86-ninja removed MSVC environment setup
The file was modifiedbuildbot/google/docker/windows-base-vscode2019/Dockerfile (diff)
The file was modifiedbuildbot/google/docker/windows-base-vscode2019/VERSION (diff)
The file was modifiedbuildbot/google/terraform/main.tf (diff)
The file was modifiedbuildbot/google/docker/buildbot-windows10-vs2019/Dockerfile (diff)
The file was modifiedbuildbot/google/docker/buildbot-windows10-vs2019/VERSION (diff)
Commit afcad9888264b073d5a16d0efe57792de51c2627 by kuhnel
fixed compiler argument

Otherwise MSVC would have been used...
The file was modifiedzorg/buildbot/builders/ClangBuilder.py (diff)

Summary

  1. [llvm-install-name-tool] Update the command-line guide (details)
  2. [NewPM] Fix pr45927.ll under NPM (details)
  3. [MemorySSA] Be more conservative when traversing MemoryPhis. (details)
  4. Support dwarf fission for wasm object files (details)
  5. [TargetRegisterInfo] Add a couple of target hooks for the greedy register allocator (details)
  6. [test] Fix FullUnroll.ll (details)
  7. [AArch64] Enable implicit null check transformation (details)
  8. [RISCV] Support Shadow Call Stack (details)
  9. [MLIR][TableGen] Automatic detection and elimination of redundant methods (details)
  10. [MemorySSA] Fix an unused variable warning [NFC] (details)
  11. [PowerPC] Implement Vector Count Mask Bits builtins in LLVM/Clang (details)
  12. [PowerPC] Add Set Boolean Condition Instruction Definitions and MC Tests (details)
  13. [AArch64][GlobalISel] clang-format AArch64LegalizerInfo.cpp. NFC. (details)
  14. [AArch64][GlobalISel] Make G_STORE <8 x s8> legal. (details)
  15. [lldb] Clarify docstring for SBBlock::IsInlined, NFC (details)
  16. [mlir][shape] Add `shape.cstr_require %bool` (details)
  17. [MLIR] Fix build failure due to https://reviews.llvm.org/D87059. (details)
  18. [scudo/standalone] Don't define test main function for Fuchsia (details)
  19. [NFC][Lsan] Fix zero-sized array compilation error (details)
  20. [NFC] clang-format one line (details)
  21. [sanitizer] Add facility to print the full StackDepot (details)
  22. [libc] Add implementation for hypotf (details)
  23. Revert "[sanitizer] Add facility to print the full StackDepot" (details)
  24. [AArch64] Emit zext move when the source of the zext is AssertZext or AssertSext (details)
  25. [X86] Add some demanded bits test cases for PDEP with constant mask (details)
  26. This is a test commit (details)
  27. Revert "This is a test commit" (details)
  28. [FPEnv] Use typed accessors in FPOptions (details)
  29. [AArch64] Add tests for zext pattern match with AssertZext/AssertSext operand, NFC (details)
  30. [NFC][fuzzer] Simplify StrcmpTest.cpp (details)
  31. Revert "[InstCombine] Canonicalize SPF_ABS to abs intrinc" (details)
  32. [sanitizer] Add facility to print the full StackDepot (details)
  33. [NFC][sanitizer] Disable a test on Windows (details)
  34. [NFC][gotsan] Fix 'format' error (details)
  35. AArch64: make sure jump table entries can reach entire image (details)
  36. [TableGen][GlobalISel] Fix handling of zero_reg (details)
  37. [SCEV] Generalize SCEVParameterRewriter to accept SCEV expression as target. (details)
  38. Revert "[libunwind] Support for leaf function unwinding." (details)
  39. Recommit "[DSE] Switch to MemorySSA-backed DSE by default." (details)
  40. [mlir][Linalg] Evolve named ops to use assembly form and support linalg on tensors. (details)
  41. [Polly] Update map passed to SCEVParameterReweriter. (details)
  42. [Test] Missing range check removal opportunity (details)
  43. [UpdateCCTestChecks] Include generated functions if asked (details)
  44. [DWARFYAML][test] Use 'CHECK-NEXT:' to make checkers stricter. NFC. (details)
  45. [DWARFYAML] Make the include_directories, file_names and opcodes fields of the line table optional. (details)
  46. [libunwind] Support for leaf function unwinding. (details)
  47. [InstSimplify] add another test for NaN propagation; NFC (details)
  48. [AMDGPU] Set DS alignment requirements to be more strict (details)
  49. [SLP] Allow reordering of vectorization trees with reused instructions. (details)
  50. Revert "[amdgpu] Lower SGPR-to-VGPR copy in the final phase of ISel." (details)
  51. emacs: Add nofree and willreturn to list of attributes (details)
  52. IR: Move denormal mode parsing from MachineFunction to Function (details)
  53. [InstSimplify] fix fmin/fmax miscompile for partial undef vectors (PR47567) (details)
  54. [mlir][StandardToSPIRV] Handle vector of i1 case for lowering zexti to SPIR-V. (details)
  55. [clangd] Add option for disabling AddUsing tweak on some namespaces. (details)
  56. [AIX] Enable large code model when building with clang (details)
  57. [DAG] BuildVectorSDNode::getSplatValue - pull out repeated getNumOperands() calls. NFCI. (details)
  58. [X86][AVX] Add missing i686 broadcastm test coverage (details)
  59. [mlir][openacc] Support Index and AnyInteger in loop op (details)
  60. [mlir][openacc] Add missing operands for acc.data operation (details)
  61. [MLIR][SPIRV] Create new ctx for deserialization in roundtrips. (details)
  62. [DFSan] Add strpbrk wrapper. (details)
  63. [X86][AVX] lowerBuildVectorAsBroadcast - improve i64 BROADCASTM lowering on 32-bit targets (details)
  64. [MLIR][ODS] Add constBuilderCall for TypeArrayAttr (details)
  65. Extending Baremetal toolchain's support for the rtlib option. (details)
  66. Use one more byte to silence a warning from Vistual C++ (details)
  67. [NFC][ScheduleDAG] Remove unused EntrySU SUnit (details)
  68. [libomptarget] Disable build of amdgpu plugin as it doesn't build with rocm. (details)
  69. [clang-format] Add a option for the position of Java static import (details)
  70. [clang-format] NFC ensure the clang-format tests remain clang-formatted (details)
  71. [mlir][shape] Extend shape.cstr_require with a message. (details)
  72. [clangd] Add Random Forest runtime for code completion. (details)
  73. [AArch64][GlobalISel] Make <8 x s8> of G_BUILD_VECTOR legal. (details)
  74. AMDGPU: Don't sometimes allow instructions before lowered si_end_cf (details)
  75. [flang] Rework preprocessing of stringification (details)
  76. [ASan][NewPM] Fix byref-args.ll under NPM (details)
  77. [Sema] Handle objc_super special lookup when checking builtin compatibility (details)
  78. DebugInfo: Tidy up initializing multi-section contributions in DWARFContext (details)
  79. [test][HWAsan] Fix kernel-inline.ll under NPM (details)
  80. [CodeGen] emit CG profile for COFF object file (details)
  81. Reapply "RegAllocFast: Record internal state based on register units" (details)
  82. RegAllocFast: Rewrite and improve (details)
  83. CodeGen: Move split block utility to MachineBasicBlock (details)
  84. [X86][AVX] Add missing non AVX512VL broadcastm test coverage (details)
  85. PR47468: Fix findPHICopyInsertPoint, so that copies aren't incorrectly inserted after an INLINEASM_BR. (details)
  86. DebugInfo: Simplify line table parsing to take all the units together, rather than CUs and TUs separately (details)
  87. Linewrap & remove some dead typedefs from previous commit (details)
  88. [InstCombine][SVE] Skip scalable type for InstCombiner::getFlippedStrictnessPredicateAndConstant. (details)
  89. [test][TSan] Fix tests under NPM (details)
  90. [X86][AVX] lowerBuildVectorAsBroadcast - improve BROADCASTM lowering on non-VLX targets (details)
  91. scudo: Add an API for disabling memory initialization per-thread. (details)
  92. First pass on MLIR python context lifetime management. (details)
  93. clangd:  Make ompletionModelCodegen.py tpy2.7 compatible (details)
  94. [gn build] (manually) port 9b6765e784b3 (details)
  95. Pre-commit test for CSEing masked loads/stores (details)
  96. [gn build] Do not sync filenames containing variable references (details)
  97. [clang-format] Recognize "hxx" as a C++ header in clang-format-diff.py (details)
  98. Temporarily Revert "[SLP] Allow reordering of vectorization trees with reused instructions." (details)
  99. [gn build] (manually) port 9b6765e784b3 more (details)
  100. [gn build] add file i forgot to add in 929d91a55616 (details)
  101. [InstSimplify] add tests for constant folding fmin/fmax with undef op; NFC (details)
  102. clang: Make changes in 7c8bb409f31e py2.7-compatible (details)
  103. CompletionModelCodegen: Remove unused import (details)
  104. [OpenMP] Initial Support for OpenMP Webpage Documentation (details)
  105. [msan][asan] Add runtime flag intercept_strcmp (details)
  106. [llvm-cov] Allow commas in filenames passed to `-object` flag (details)
  107. [COFF] Move per-global .drective emission from AsmPrinter to TLOFCOFF (details)
  108. [spirv] Move device info from resource limit into target env (details)
  109. Temporarily Revert "[clangd] Add Random Forest runtime for code completion." (details)
  110. [test][InstrProf] Fix always_inline.ll under NPM (details)
  111. [instcombine][x86] Converted pdep/pext with shifted mask to simple arithmetic (details)
  112. [clang][module] Improve incomplete-umbrella warning (details)
  113. [clang] Remove profile available check for fsplit-machine-functions. (details)
  114. [NFC][sanitizer] Don't use ::testing::internal (details)
  115. [lld][WebAssembly] Fix -Wunused-variable after D87663 (details)
  116. [PowerPC] Implement Move to VSR Mask builtins in LLVM/Clang (details)
  117. [GlobalISel] Add lowering support for G_ABS and use for AArch64. (details)
  118. [SCEV] Fix an unused variable in -DLLVM_ENABLE_ASSERTIONS=off build (details)
  119. [NFC][Asan] Fix test broken by RegAllocFast (details)
  120. [NFC][StackSafety] Replace auto with type (details)
  121. [AArch64][GlobalISel] Legalize arithmetic ops for <4 x s16> (details)
  122. [AArch64][GlobalISel] Add tests for pre-existing selection support for <4 x s16> arithmetic/bitwise ops. (details)
  123. [NFC][LSan] Add REQUIRES: linux (details)
  124. [LiveDebugValues] Add `#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)` to suppress -Wunused-function (details)
Commit 53ba045f488f7ef7d4894926fad8de0b76f1e20a by alexshap
[llvm-install-name-tool] Update the command-line guide
The file was modifiedllvm/docs/CommandGuide/llvm-install-name-tool.rst
Commit 179a22e807a40ae5821920cec3c1933eef4dc30c by aeubanks
[NewPM] Fix pr45927.ll under NPM
The file was modifiedllvm/test/Analysis/MemorySSA/pr45927.ll
Commit a0017c2bc258690146f18491317144e487ddb101 by flo
[MemorySSA] Be more conservative when traversing MemoryPhis.

I think we need to be even more conservative when traversing memory
phis, to make sure we catch any loop carried dependences.

This approach updates fillInCurrentPair to use unknown sizes for
locations when we walk over a phi, unless the location is guaranteed to
be loop-invariant for any possible loop. Using an unknown size for
locations should ensure we catch all memory accesses to locations after
the given memory location, which includes loop-carried dependences.

Reviewed By: asbirlea

Differential Revision: https://reviews.llvm.org/D87778
The file was modifiedllvm/test/Analysis/MemorySSA/phi-translation.ll
The file was modifiedllvm/include/llvm/Analysis/MemorySSA.h
Commit 0ff28fa6a75617d61b1aeea77463d6a1684c3c89 by dschuff
Support dwarf fission for wasm object files

Initial support for dwarf fission sections (-gsplit-dwarf) on wasm.
The most interesting change is support for writing 2 files (.o and .dwo) in the
wasm object writer. My approach moves object-writing logic into its own function
and calls it twice, swapping out the endian::Writer (W) in between calls.
It also splits the import-preparation step into its own function (and skips it when writing a dwo).

Differential Revision: https://reviews.llvm.org/D85685
The file was addedllvm/test/DebugInfo/WebAssembly/fission-cu.ll
The file was modifiedllvm/lib/MC/MCAsmBackend.cpp
The file was modifiedllvm/lib/MC/WasmObjectWriter.cpp
The file was modifiedllvm/lib/MC/MCObjectFileInfo.cpp
The file was modifiedclang/test/Driver/split-debug.c
The file was modifiedllvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
The file was modifiedllvm/include/llvm/MC/MCWasmObjectWriter.h
The file was modifiedclang/lib/Driver/ToolChains/Clang.cpp
The file was addedllvm/test/DebugInfo/WebAssembly/fission-sections.ll
Commit 99e865b618f31c69776273a60addbd88917a29d9 by qcolombet
[TargetRegisterInfo] Add a couple of target hooks for the greedy register allocator

Before this patch, the last chance recoloring and deferred spilling
techniques were solely controled by command line options.
This patch adds target hooks for these two techniques so that it
is easier for backend writers to override the default behavior.

The default behavior of the hooks preserves the default values of
the related command line options.

NFC
The file was modifiedllvm/include/llvm/CodeGen/TargetRegisterInfo.h
The file was modifiedllvm/lib/CodeGen/RegAllocGreedy.cpp
Commit f2f0474c93ee67421fae007528ae4be20ae384f8 by aeubanks
[test] Fix FullUnroll.ll

I believe the intention of this test added in
https://reviews.llvm.org/D71687 was to test LoopFullUnrollPass with
clang's -fno-unroll-loops, not its interaction with optnone. Loop
unrolling passes don't run under optnone/-O0.

Also added back unintentionally removed -disable-loop-unrolling from
https://reviews.llvm.org/D85578.

Reviewed By: echristo

Differential Revision: https://reviews.llvm.org/D86485
The file was modifiedllvm/test/Transforms/LoopUnroll/FullUnroll.ll
Commit b04c181ed776c344e6f5e2653a22bc6e5746834a by listmail
[AArch64] Enable implicit null check transformation

This change enables the generic implicit null transformation for the AArch64 target. As background for those unfamiliar with our implicit null check support:

    An implicit null check is the use of a signal handler to catch and redirect to a handler a null pointer. Specifically, it's replacing an explicit conditional branch with such a redirect. This is only done for very cold branches under frontend control w/appropriate metadata.
    FAULTING_OP is used to wrap the faulting instruction. It is modelled as being a conditional branch to reflect the fact it can transfer control in the CFG.
    FAULTING_OP does not need to be an analyzable branch to achieve it's purpose. (Or at least, that's the x86 model. I find this slightly questionable.)
    When lowering to MC, we convert the FAULTING_OP back into the actual instruction, record the labels, and lower the original instruction.

As can be seen in the test changes, currently the AArch64 backend does not eliminate the unconditional branch to the fallthrough block. I've tried two approaches, neither of which worked. I plan to return to this in a separate change set once I've wrapped my head around the interactions a bit better. (X86 handles this via AllowModify on analyzeBranch, but adding the obvious code causing BranchFolding to crash. I haven't yet figured out if it's a latent bug in BranchFolding, or something I'm doing wrong.)

Differential Revision: https://reviews.llvm.org/D87851
The file was modifiedllvm/test/CodeGen/AArch64/implicit-null-check.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.cpp
The file was modifiedllvm/lib/CodeGen/BranchRelaxation.cpp
The file was modifiedllvm/lib/CodeGen/ImplicitNullChecks.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.h
Commit 1c466477ad468d8a18c43b738df7b7fc6213e9a8 by zhaoshiz
[RISCV] Support Shadow Call Stack

Currenlty assume x18 is used as pointer to shadow call stack. User shall pass
flags:

"-fsanitize=shadow-call-stack -ffixed-x18"

Runtime supported is needed to setup x18.

If SCS is desired, all parts of the program should be built with -ffixed-x18 to
maintain inter-operatability.

There's no particuluar reason that we must use x18 as SCS pointer. Any register
may be used, as long as it does not have designated purpose already, like RA or
passing call arguments.

Differential Revision: https://reviews.llvm.org/D84414
The file was modifiedllvm/lib/Target/RISCV/RISCVFrameLowering.cpp
The file was modifiedllvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h
The file was modifiedllvm/lib/Target/RISCV/Utils/RISCVBaseInfo.cpp
The file was modifiedclang/lib/Driver/SanitizerArgs.cpp
The file was modifiedclang/test/Driver/sanitizer-ld.c
The file was modifiedclang/test/CodeGen/shadowcallstack-attr.c
The file was modifiedclang/lib/Driver/ToolChain.cpp
The file was addedllvm/test/CodeGen/RISCV/shadowcallstack.ll
Commit 8069844577d47f503cb71644f2e58e0237d5b539 by jurahul
[MLIR][TableGen] Automatic detection and elimination of redundant methods

- Change OpClass new method addition to find and eliminate any existing methods that
  are made redundant by the newly added method, as well as detect if the newly added
  method will be redundant and return nullptr in that case.
- To facilitate that, add the notion of resolved and unresolved parameters, where resolved
  parameters have each parameter type known, so that redundancy checks on methods
  with same name but different parameter types can be done.
- Eliminate existing code to avoid adding conflicting/redundant build methods and rely
  on this new mechanism to eliminate conflicting build methods.

Fixes https://bugs.llvm.org/show_bug.cgi?id=47095

Differential Revision: https://reviews.llvm.org/D87059
The file was modifiedmlir/lib/TableGen/OpClass.cpp
The file was modifiedmlir/test/mlir-tblgen/op-attribute.td
The file was modifiedmlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
The file was modifiedmlir/include/mlir/TableGen/OpClass.h
The file was modifiedmlir/tools/mlir-tblgen/OpFormatGen.cpp
The file was modifiedmlir/test/mlir-tblgen/op-result.td
Commit b4013f9c7febe70bddca16fb80a2e99623528871 by listmail
[MemorySSA] Fix an unused variable warning [NFC]
The file was modifiedllvm/include/llvm/Analysis/MemorySSA.h
Commit 2c3bc918db35913437e9302b77b11c08eb3ea6e4 by amy.kwan1
[PowerPC] Implement Vector Count Mask Bits builtins in LLVM/Clang

This patch implements the vec_cntm function prototypes in altivec.h in order to
utilize the vector count mask bits instructions introduced in Power10.

Differential Revision: https://reviews.llvm.org/D82726
The file was modifiedclang/test/CodeGen/builtins-ppc-p10vector.c
The file was modifiedclang/include/clang/Basic/BuiltinsPPC.def
The file was modifiedllvm/test/CodeGen/PowerPC/p10-vector-mask-ops.ll
The file was modifiedllvm/include/llvm/IR/IntrinsicsPowerPC.td
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrPrefix.td
The file was modifiedclang/lib/Headers/altivec.h
Commit 6f3c0991bf9be48bd18a324c90e4cfcd37f82b96 by amy.kwan1
[PowerPC] Add Set Boolean Condition Instruction Definitions and MC Tests

This patch adds the instruction definitions and assembly/disassembly tests for
the set boolean condition instructions. This also includes the negative, and
reverse variants of the instruction.

Differential Revision: https://reviews.llvm.org/D86252
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrPrefix.td
The file was modifiedllvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt
The file was modifiedllvm/test/MC/PowerPC/ppc64-encoding-ISA31.s
Commit 196e2f97b714bb535a39a2daa949e523c21c0269 by Amara Emerson
[AArch64][GlobalISel] clang-format AArch64LegalizerInfo.cpp. NFC.
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
Commit f5898f8c2def7a1897559a7454086243b7e9ebb6 by Amara Emerson
[AArch64][GlobalISel] Make G_STORE <8 x s8> legal.
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
Commit 4926a5ee63017396e1c55b1505f9fd2bed858218 by Vedant Kumar
[lldb] Clarify docstring for SBBlock::IsInlined, NFC

Previously, there was a little ambiguity about whether IsInlined should
return true for an inlined lexical block, since technically the lexical
block would not represent an inlined function (it'd just be contained
within one).

Edit suggested by Jim Ingham.
The file was modifiedlldb/bindings/interface/SBBlock.i
Commit bae63742057785e03732f58d6ed1ec7bda090cc1 by silvasean
[mlir][shape] Add `shape.cstr_require %bool`

This op is a catch-all for creating witnesses from various random kinds
of constraints. In particular, I when dealing with extents directly,
which are of `index` type, one can directly use std ops for calculating
the predicates, and then use cstr_require for the final conversion to a
witness.

Differential Revision: https://reviews.llvm.org/D87871
The file was modifiedmlir/lib/Dialect/Shape/IR/Shape.cpp
The file was modifiedmlir/test/Dialect/Shape/ops.mlir
The file was modifiedmlir/include/mlir/Dialect/Shape/IR/ShapeOps.td
The file was modifiedmlir/test/Dialect/Shape/canonicalize.mlir
Commit ea237e2c8e5d082715effb9cb64158d7c6894e27 by jurahul
[MLIR] Fix build failure due to https://reviews.llvm.org/D87059.

- Remove spurious ;
- Make comparison object invokable as const.

Differential Revision: https://reviews.llvm.org/D87872
The file was modifiedmlir/include/mlir/TableGen/OpClass.h
Commit 27f34540ea56207f527dba6bbb9cd25a57be3f62 by mcgrathr
[scudo/standalone] Don't define test main function for Fuchsia

Fuchsia's unit test library provides the main function by default.

Reviewed By: cryptoad

Differential Revision: https://reviews.llvm.org/D87809
The file was modifiedcompiler-rt/lib/scudo/standalone/tests/scudo_unit_test_main.cpp
Commit 03358becbf22a221d6d965ec8f3f7068668f7d29 by Vitaly Buka
[NFC][Lsan] Fix zero-sized array compilation error
The file was modifiedclang/lib/Tooling/Syntax/Synthesis.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_stoptheworld_linux_libcdep.cpp
Commit 55edf7039e22312790ac950305746262d2856d97 by Vitaly Buka
[NFC] clang-format one line
The file was modifiedclang/lib/Tooling/Syntax/Synthesis.cpp
Commit 2ffaa9a1732c6f2af514603d25f0e8c238b3dd06 by tejohnson
[sanitizer] Add facility to print the full StackDepot

Split out of D87120 (memory profiler). Added unit testing of the new
printing facility.

Differential Revision: https://reviews.llvm.org/D87792
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_stackdepotbase.h
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_stackdepot.h
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_stackdepot.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/tests/sanitizer_stackdepot_test.cpp
Commit f55963d501e46c9453d08a0c764ec40141230966 by lntue
[libc] Add implementation for hypotf

Truncating the sum of squares, and then use shift-and-add algorithm to compute its square root.
Required MPFR testing infra is updated in https://reviews.llvm.org/D87514

Differential Revision: https://reviews.llvm.org/D87516
The file was modifiedlibc/config/linux/api.td
The file was addedlibc/test/src/math/hypotf_test.cpp
The file was modifiedlibc/src/math/CMakeLists.txt
The file was addedlibc/src/math/hypotf.cpp
The file was addedlibc/src/math/hypotf.h
The file was modifiedlibc/config/linux/aarch64/entrypoints.txt
The file was modifiedlibc/config/linux/x86_64/entrypoints.txt
The file was modifiedlibc/spec/stdc.td
The file was modifiedlibc/test/src/math/CMakeLists.txt
Commit 6e475e1288e3e924643a10a426707d704783fcd5 by tejohnson
Revert "[sanitizer] Add facility to print the full StackDepot"

This reverts commit 2ffaa9a1732c6f2af514603d25f0e8c238b3dd06.

There were 2 reported bot failures that need more investigation:

http://lab.llvm.org:8011/builders/sanitizer-windows/builds/69871/steps/stage%201%20check/logs/stdio

   This one is in my new test.

http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fuzzer/builds/39187/steps/check-fuzzer/logs/stdio

   This one seems completely unrelated.
The file was modifiedcompiler-rt/lib/sanitizer_common/tests/sanitizer_stackdepot_test.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_stackdepot.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_stackdepotbase.h
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_stackdepot.h
Commit 992698cfbc898c556fa98962540bd273b115e35c by weiwei64
[AArch64] Emit zext move when the source of the zext is AssertZext or AssertSext

When the source of the zext is AssertZext or AssertSext, it is hard to know any information about the upper 32 bits,
so we should insert a zext move before emitting SUBREG_TO_REG to define the lower 32 bits.

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D87771
The file was modifiedllvm/test/CodeGen/AArch64/shift_minsize.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.h
Commit fb92f863f6849c7fa01f5487bd09544ee0856c59 by craig.topper
[X86] Add some demanded bits test cases for PDEP with constant mask

The number of ones in the mask for the PDEP determines how many
bits of the other operand are used. If the mask is constant we
can use this to build a mask for SimplifyDemandedBits. This can
be used to replace the extends in the test with anyextend.
The file was modifiedllvm/test/CodeGen/X86/bmi2-x86_64.ll
The file was modifiedllvm/test/CodeGen/X86/bmi2.ll
Commit 9d54b166c2e59f29e476a6566951b6809fc8808e by artur.bialas
This is a test commit
The file was modifiedREADME.md
Commit 5a733468e09482b442da1a20aa083d2939f4d136 by artur.bialas
Revert "This is a test commit"

This reverts commit 9d54b166c2e59f29e476a6566951b6809fc8808e.
The file was modifiedREADME.md
Commit 8a86261c511e09629aa48c13cb84172b9be26c0c by sepavloff
[FPEnv] Use typed accessors in FPOptions

Previously methods `FPOptions::get*` returned unsigned value even if the
corresponding property was represented by specific enumeration type. With
this change such methods return actual type of the property. It also
allows printing value of a property as text rather than integer code.

Differential Revision: https://reviews.llvm.org/D87812
The file was modifiedllvm/include/llvm/ADT/FloatingPointMode.h
The file was modifiedclang/include/clang/Basic/LangOptions.h
The file was modifiedclang/test/AST/ast-dump-fpfeatures.cpp
The file was modifiedclang/include/clang/Basic/FPOptions.def
Commit 8f09cec8c999a739991f988945159ff9665d50c8 by weiwei64
[AArch64] Add tests for zext pattern match with AssertZext/AssertSext operand, NFC
The file was addedllvm/test/CodeGen/AArch64/arm64-assert-zext-sext.ll
Commit f16c4a3704f26d8f557856b7c9f3ce73c1bf1a31 by Vitaly Buka
[NFC][fuzzer] Simplify StrcmpTest.cpp

The test started to consistently fail after unrelated
2ffaa9a1732c6f2af514603d25f0e8c238b3dd06.

Even before the patch it was possible to fail the test,
e.g. -seed=1660180256 on my workstation.

Also this checks do not look related to strcmp.
The file was modifiedcompiler-rt/test/fuzzer/StrcmpTest.cpp
Commit 13e19d2e7cdc2a54bb85da702df47c8a04a6d857 by nikita.ppv
Revert "[InstCombine] Canonicalize SPF_ABS to abs intrinc"

This reverts commit 05d4c4ebc2fb006b8a2bd05b24c6aba10dd2eef8.

mstorsjo reports a miscompile after this change in
https://reviews.llvm.org/D87188#2281093. Reverting until I can
investigate this.
The file was modifiedllvm/test/Transforms/InstCombine/select_meta.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
The file was modifiedllvm/test/Transforms/InstCombine/abs_abs.ll
The file was modifiedclang/test/CodeGen/builtins-wasm.c
The file was modifiedllvm/test/Transforms/PhaseOrdering/X86/vector-reductions.ll
The file was modifiedllvm/test/Transforms/PhaseOrdering/min-max-abs-cse.ll
The file was modifiedllvm/test/Transforms/InstCombine/max-of-nots.ll
The file was modifiedllvm/test/Transforms/InstCombine/abs-1.ll
The file was modifiedllvm/test/Transforms/InstCombine/icmp.ll
The file was modifiedllvm/test/Transforms/InstCombine/sub-of-negatible.ll
The file was modifiedllvm/test/Transforms/InstCombine/call-callconv.ll
The file was modifiedllvm/test/Transforms/InstCombine/cttz-abs.ll
Commit a90229d6cee8910505999678ed137a7f0f9083ed by Vitaly Buka
[sanitizer] Add facility to print the full StackDepot

Split out of D87120 (memory profiler). Added unit testing of the new
printing facility.

Reviewed By: vitalybuka

Differential Revision: https://reviews.llvm.org/D87792
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_stackdepot.h
The file was modifiedcompiler-rt/lib/sanitizer_common/tests/CMakeLists.txt
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_stackdepotbase.h
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_stackdepot.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/tests/sanitizer_stackdepot_test.cpp
Commit e259f7b88266572aaf00cfc1ff7fe88a9fdb1c7a by Vitaly Buka
[NFC][sanitizer] Disable a test on Windows
The file was modifiedcompiler-rt/lib/sanitizer_common/tests/sanitizer_stackdepot_test.cpp
Commit c0e7f64685789520ad732d9dd6bf388dc916e518 by Vitaly Buka
[NFC][gotsan] Fix 'format' error
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_stoptheworld_linux_libcdep.cpp
Commit 2afe4becec77d91b47afcc4b6eaaa1002cebf837 by Tim Northover
AArch64: make sure jump table entries can reach entire image

This turns all jump table entries into deltas within the target
function because in the small memory model all code & static data must
be in a 4GB block somewhere in memory.

When the entries were a delta between the table location and a basic
block, the 32-bit signed entries are not enough to guarantee
reachability.

https://reviews.llvm.org/D87286
The file was modifiedllvm/test/CodeGen/AArch64/jump-table-exynos.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.td
The file was modifiedllvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
The file was addedllvm/test/CodeGen/AArch64/jump-table-duplicate.mir
The file was modifiedllvm/test/CodeGen/AArch64/win64-jumptable.ll
The file was modifiedllvm/test/CodeGen/AArch64/jump-table.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
Commit c10200536f2ee3f29a7d2b82812e5d13b40fc3e4 by bjorn.a.pettersson
[TableGen][GlobalISel] Fix handling of zero_reg

When generating matching tables for GlobalISel, TableGen would output
"::zero_reg" whenever encountering the zero_reg, which in turn would
result in compilation error. This patch fixes that by instead outputting
NoRegister (== 0), which is the same result that TableGen produces when
generating matching tables for ISelDAG.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D86215
The file was modifiedllvm/lib/Target/ARM/ARMInstructionSelector.cpp
The file was modifiedllvm/utils/TableGen/GlobalISelEmitter.cpp
The file was addedllvm/test/TableGen/GlobalISelEmitter-zero-reg.td
The file was modifiedllvm/utils/TableGen/CodeGenTarget.cpp
The file was modifiedllvm/utils/TableGen/CodeGenTarget.h
Commit 4635f6050b105f13138ca6d7a85ae797415803a0 by flo
[SCEV] Generalize SCEVParameterRewriter to accept SCEV expression as target.

This patch extends SCEVParameterRewriter to support rewriting unknown
epxressions to arbitrary SCEV expressions. It will be used by further
patches.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D67176
The file was modifiedllvm/include/llvm/Analysis/ScalarEvolutionExpressions.h
The file was modifiedllvm/lib/Analysis/ScalarEvolutionDivision.cpp
The file was modifiedllvm/unittests/Analysis/ScalarEvolutionTest.cpp
Commit 5831adb8c38f3fd1b17ff52984c514fc32e893f6 by daniel.kiss
Revert "[libunwind] Support for leaf function unwinding."

This reverts commit 23bef7ee9923b1262326981960397e8cd95d6923.
The file was modifiedlibunwind/src/DwarfParser.hpp
The file was removedlibunwind/test/unwind_leaffunction.pass.cpp
The file was removedlibunwind/test/signal_unwind.pass.cpp
The file was modifiedlibunwind/src/DwarfInstructions.hpp
The file was modifiedlibunwind/test/lit.site.cfg.in
Commit 9d172c8e9c845a36b61dc12c27de8acdbef8b247 by flo
Recommit "[DSE] Switch to MemorySSA-backed DSE by default."

This switches to using DSE + MemorySSA by default again, after
fixing the issues reported after the first commit.

Notable fixes fc8200633122, a0017c2bc258.

This reverts commit 3a59628f3cc26eb085acfc9cbdc97243ef71a6c5.
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/cs-cs-aliasing.ll
The file was modifiedllvm/test/Other/opt-O3-pipeline-enable-matrix.ll
The file was modifiedllvm/test/Transforms/Coroutines/ArgAddr.ll
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/calloc-store.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/opt-pipeline.ll
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/2011-03-25-DSEMiscompile.ll
The file was modifiedllvm/test/Other/new-pm-thinlto-defaults.ll
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/combined-partial-overwrites.ll
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/pr11390.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-retcon.ll
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/multiblock-captures.ll
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/noop-stores.ll
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/memset-missing-debugloc.ll
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/lifetime.ll
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/dominate.ll
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/debug-counter.ll
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/merge-stores.ll
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/simple.ll
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/2011-09-06-MemCpy.ll
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/atomic-overlapping.ll
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/invariant.start.ll
The file was modifiedllvm/test/Other/new-pm-lto-defaults.ll
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/multiblock-throwing.ll
The file was modifiedllvm/lib/Transforms/Scalar/DeadStoreElimination.cpp
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/mda-with-dbg-values.ll
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/overlap.ll
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/memintrinsics.ll
The file was modifiedllvm/test/Transforms/MemCpyOpt/memcpy.ll
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/const-pointers.ll
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/int_sideeffect.ll
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/OverwriteStoreEnd.ll
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/memset-and-memcpy.ll
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/simple-todo.ll
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/free.ll
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/2016-07-17-UseAfterFree.ll
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/atomic.ll
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/atomic-todo.ll
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/debuginfo.ll
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/inst-limits.ll
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/multiblock-exceptions.ll
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/tail-byval.ll
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/operand-bundles.ll
The file was modifiedclang/test/CodeGen/thinlto-distributed-newpm.ll
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/multiblock-multipath.ll
The file was modifiedllvm/test/Analysis/BasicAA/modref.ll
The file was modifiedllvm/test/Other/new-pm-defaults.ll
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/PartialStore.ll
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/X86/gather-null-pointer.ll
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/fence-todo.ll
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/merge-stores-big-endian.ll
The file was modifiedclang/test/CodeGenObjC/exceptions.m
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/no-targetdata.ll
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/multiblock-simple.ll
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/memoryssa-scan-limit.ll
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/2011-09-06-EndOfFunction.ll
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/memcpy-complete-overwrite.ll
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/multiblock-malloc-free.ll
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/multiblock-partial.ll
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/multiblock-unreachable.ll
The file was modifiedllvm/test/Other/opt-O2-pipeline.ll
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/OverwriteStoreBegin.ll
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/launder.invariant.group.ll
The file was modifiedllvm/test/Other/opt-O3-pipeline.ll
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/crash.ll
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/multiblock-memintrinsics.ll
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/stats.ll
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/PartialStore2.ll
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/multiblock-loops.ll
The file was modifiedllvm/test/Other/opt-Os-pipeline.ll
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/pr47285-not-overwritten-on-all-exit-paths.ll
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/fence.ll
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/multiblock-multipath-throwing.ll
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/libcalls.ll
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/simple-preservation.ll
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/multiblock-memoryphis.ll
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/memset-unknown-sizes.ll
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/multiblock-overlap.ll
Commit 93fd30bac3345fea4f5beba3241f1ef4f2f5f419 by ntv
[mlir][Linalg] Evolve named ops to use assembly form and support linalg on tensors.

This revision allows representing a reduction at the level of linalg on tensors for named ops. When a structured op has a reduction and returns tensor(s), new conventions are added and documented.

As an illustration, the syntax for a `linalg.matmul` writing into a buffer is:

```
  linalg.matmul ins(%a, %b : memref<?x?xf32>, tensor<?x?xf32>)
               outs(%c : memref<?x?xf32>)
```

, whereas the syntax for a `linalg.matmul` returning a new tensor is:

```
  %d = linalg.matmul ins(%a, %b : tensor<?x?xf32>, memref<?x?xf32>)
                    init(%c : memref<?x?xf32>)
                      -> tensor<?x?xf32>
```

Other parts of linalg will be extended accordingly to allow mixed buffer/tensor semantics in the presence of reductions.
The file was modifiedmlir/test/Dialect/Linalg/loops.mlir
The file was modifiedmlir/integration_test/Dialect/Linalg/CPU/test-conv-2d-nchw-call.mlir
The file was modifiedmlir/test/Dialect/Linalg/transform-patterns-matmul-to-vector.mlir
The file was modifiedmlir/test/Conversion/LinalgToVector/linalg-to-vector.mlir
The file was modifiedmlir/test/Dialect/Linalg/invalid.mlir
The file was modifiedmlir/test/lib/Dialect/Test/TestDialect.cpp
The file was modifiedmlir/include/mlir/IR/OpBase.td
The file was modifiedmlir/integration_test/Dialect/Linalg/CPU/test-conv-3d-ndhwc-call.mlir
The file was modifiedmlir/test/Dialect/Linalg/promote.mlir
The file was modifiedmlir/integration_test/Dialect/Linalg/CPU/test-conv-1d-call.mlir
The file was modifiedmlir/test/Dialect/Linalg/fusion.mlir
The file was modifiedmlir/include/mlir/Dialect/Linalg/IR/LinalgOps.h
The file was modifiedmlir/test/IR/slice.mlir
The file was modifiedmlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
The file was modifiedmlir/test/Dialect/Linalg/standard.mlir
The file was modifiedmlir/integration_test/Dialect/Linalg/CPU/test-conv-3d-call.mlir
The file was modifiedmlir/test/Dialect/Linalg/tile-and-distribute.mlir
The file was modifiedmlir/test/Dialect/Linalg/transform-patterns.mlir
The file was modifiedmlir/docs/OpDefinitions.md
The file was modifiedmlir/tools/mlir-linalg-ods-gen/mlir-linalg-ods-gen.cpp
The file was modifiedmlir/include/mlir/Dialect/Linalg/IR/LinalgStructuredOps.td
The file was modifiedmlir/test/mlir-linalg-ods-gen/test-linalg-ods-gen.tc
The file was modifiedmlir/include/mlir/Dialect/Linalg/IR/LinalgTraits.h
The file was modifiedmlir/test/Dialect/Linalg/tile_parallel_reduce.mlir
The file was modifiedmlir/test/mlir-cpu-runner/linalg_integration_test.mlir
The file was modifiedmlir/include/mlir/Dialect/Shape/IR/ShapeBase.td
The file was modifiedmlir/tools/mlir-tblgen/OpFormatGen.cpp
The file was modifiedmlir/test/Dialect/Linalg/fold-affine-min-scf.mlir
The file was modifiedmlir/test/Dialect/Linalg/promotion_options.mlir
The file was modifiedmlir/integration_test/Dialect/Linalg/CPU/test-conv-1d-ncw-call.mlir
The file was modifiedmlir/test/mlir-tblgen/op-format-spec.td
The file was modifiedmlir/test/Dialect/Linalg/canonicalize.mlir
The file was modifiedmlir/test/mlir-tblgen/op-format.mlir
The file was modifiedmlir/docs/Dialects/Linalg.md
The file was modifiedmlir/test/Dialect/Linalg/tile.mlir
The file was modifiedmlir/integration_test/Dialect/Linalg/CPU/test-conv-2d-call.mlir
The file was modifiedmlir/include/mlir/Dialect/Linalg/IR/LinalgStructuredOpsInterface.td
The file was modifiedmlir/integration_test/Dialect/Linalg/CPU/test-conv-1d-nwc-call.mlir
The file was modifiedmlir/lib/Dialect/Linalg/IR/LinalgTypes.cpp
The file was modifiedmlir/integration_test/Dialect/Linalg/CPU/test-conv-2d-nhwc-call.mlir
The file was modifiedmlir/test/Dialect/Linalg/affine.mlir
The file was modifiedmlir/test/lib/Dialect/Test/TestOps.td
The file was modifiedmlir/integration_test/Dialect/Linalg/CPU/test-conv-3d-ncdhw-call.mlir
The file was modifiedmlir/test/Dialect/Linalg/fusion-2-level.mlir
The file was modifiedmlir/test/Dialect/Linalg/roundtrip.mlir
Commit 762fbbe536996acf7175b551ce0e2c310165b135 by flo
[Polly] Update map passed to SCEVParameterReweriter.

The type of the map the SCEVParameterRewriter takes has been changed in
4635f6050b10.

Update the single use in polly to use SCEV* as type of the values.
The file was modifiedpolly/lib/CodeGen/IslExprBuilder.cpp
Commit 09a3737384ec34c6b216e7c6b9ca768c26ffb1d1 by mkazantsev
[Test] Missing range check removal opportunity
The file was addedllvm/test/Transforms/IndVarSimplify/checks_against_min_value.ll
Commit 7c8bb409f31ebbe24ac978e123efcef961a58340 by David A Greene
[UpdateCCTestChecks] Include generated functions if asked

Add the --include-generated-funcs option to update_cc_test_checks.py so that any
functions created by the compiler that don't exist in the source will also be
checked.

We need to maintain the output order of generated function checks so that
CHECK-LABEL works properly.  To do so, maintain a list of functions output for
each prefix in the order they are output.  Use this list to output checks for
generated functions in the proper order.

Differential Revision: https://reviews.llvm.org/D83004
The file was addedllvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/wasm_generated_funcs.ll.nogenerated.expected
The file was addedllvm/test/tools/UpdateTestChecks/update_llc_test_checks/arm_generated_funcs.test
The file was addedllvm/test/tools/UpdateTestChecks/update_llc_test_checks/msp430_generated_funcs.test
The file was addedllvm/test/tools/UpdateTestChecks/update_test_checks/generated_funcs.test
The file was addedllvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/lanai_generated_funcs.ll.generated.expected
The file was addedllvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/ppc_generated_funcs.ll
The file was addedllvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/wasm_generated_funcs.ll
The file was addedllvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/msp430_generated_funcs.ll
The file was addedllvm/test/tools/UpdateTestChecks/update_llc_test_checks/systemz_generated_funcs.test
The file was addedllvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/systemz_generated_funcs.ll.nogenerated.expected
The file was addedllvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/mips_generated_funcs.ll.generated.expected
The file was addedllvm/test/tools/UpdateTestChecks/update_llc_test_checks/lanai_generated_funcs.test
The file was addedllvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/lanai_generated_funcs.ll
The file was modifiedllvm/utils/UpdateTestChecks/asm.py
The file was addedllvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/arm_generated_funcs.ll.nogenerated.expected
The file was addedllvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/aarch64_generated_funcs.ll.generated.expected
The file was addedllvm/test/tools/UpdateTestChecks/update_llc_test_checks/aarch64_generated_funcs.test
The file was addedllvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/systemz_generated_funcs.ll.generated.expected
The file was addedllvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/aarch64_generated_funcs.ll
The file was addedllvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/hexagon_generated_funcs.ll
The file was addedllvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/riscv_generated_funcs.ll.nogenerated.expected
The file was addedllvm/test/tools/UpdateTestChecks/update_llc_test_checks/x86_generated_funcs.test
The file was addedllvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/aarch64_generated_funcs.ll.nogenerated.expected
The file was addedllvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/generated_funcs.ll
The file was modifiedllvm/utils/update_test_checks.py
The file was addedllvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/arm_generated_funcs.ll.generated.expected
The file was addedclang/test/utils/update_cc_test_checks/generated-funcs.test
The file was addedclang/test/utils/update_cc_test_checks/Inputs/generated-funcs.c.generated.expected
The file was addedllvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_generated_funcs.ll.generated.expected
The file was modifiedllvm/utils/UpdateTestChecks/common.py
The file was addedllvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/arm_generated_funcs.ll
The file was addedllvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/hexagon_generated_funcs.ll.generated.expected
The file was addedllvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/mips_generated_funcs.ll.nogenerated.expected
The file was addedllvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/hexagon_generated_funcs.ll.nogenerated.expected
The file was addedllvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/msp430_generated_funcs.ll.generated.expected
The file was addedllvm/test/tools/UpdateTestChecks/update_llc_test_checks/wasm_generated_funcs.test
The file was addedllvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/lanai_generated_funcs.ll.nogenerated.expected
The file was addedllvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/generated_funcs.ll.nogenerated.expected
The file was addedllvm/test/tools/UpdateTestChecks/update_llc_test_checks/amdgpu_generated_funcs.test
The file was addedllvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/sparc_generated_funcs.ll.nogenerated.expected
The file was addedllvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/ppc_generated_funcs.ll.generated.expected
The file was addedclang/test/utils/update_cc_test_checks/Inputs/generated-funcs.c.no-generated.expected
The file was addedllvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/riscv_generated_funcs.ll
The file was addedllvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/riscv_generated_funcs.ll.generated.expected
The file was addedllvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/sparc_generated_funcs.ll.generated.expected
The file was addedllvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_generated_funcs.ll
The file was addedllvm/test/tools/UpdateTestChecks/update_llc_test_checks/hexagon_generated_funcs.test
The file was addedllvm/test/tools/UpdateTestChecks/update_llc_test_checks/ppc_generated_funcs.test
The file was modifiedllvm/utils/update_cc_test_checks.py
The file was addedllvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/msp430_generated_funcs.ll.nogenerated.expected
The file was addedllvm/test/tools/UpdateTestChecks/update_llc_test_checks/riscv_generated_funcs.test
The file was addedllvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/ppc_generated_funcs.ll.nogenerated.expected
The file was addedllvm/test/tools/UpdateTestChecks/update_llc_test_checks/mips_generated_funcs.test
The file was addedllvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/generated_funcs.ll.generated.expected
The file was addedllvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86_generated_funcs.ll.generated.expected
The file was addedllvm/test/tools/UpdateTestChecks/update_llc_test_checks/sparc_generated_funcs.test
The file was addedllvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/mips_generated_funcs.ll
The file was addedllvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/systemz_generated_funcs.ll
The file was addedllvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/wasm_generated_funcs.ll.generated.expected
The file was addedllvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86_generated_funcs.ll
The file was addedllvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_generated_funcs.ll.nogenerated.expected
The file was addedclang/test/utils/update_cc_test_checks/Inputs/generated-funcs.c
The file was addedllvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/sparc_generated_funcs.ll
The file was addedllvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86_generated_funcs.ll.nogenerated.expected
The file was modifiedllvm/utils/update_llc_test_checks.py
Commit a761e81e2202e6d7ccdf07736942723c95614d7d by Xing
[DWARFYAML][test] Use 'CHECK-NEXT:' to make checkers stricter. NFC.

This patch makes checkers stricter so that we are able to avoid
some potential problems earlier.

Reviewed By: jhenderson, MaskRay

Differential Revision: https://reviews.llvm.org/D87876
The file was modifiedllvm/test/ObjectYAML/MachO/DWARF-pubsections.yaml
The file was modifiedllvm/test/ObjectYAML/MachO/DWARF-debug_line.yaml
Commit 2d35092cd2589dffbca1e34a3dc68f6df75818a9 by Xing
[DWARFYAML] Make the include_directories, file_names and opcodes fields of the line table optional.

This patch makes the include_directories, file_names and opcodes fields
of the line table optional. This helps us simplify some tests.

Reviewed By: jhenderson

Differential Revision: https://reviews.llvm.org/D87878
The file was modifiedllvm/test/ObjectYAML/MachO/DWARF-debug_line.yaml
The file was modifiedllvm/test/tools/llvm-objcopy/MachO/Inputs/strip-all-with-dwarf.yaml
The file was modifiedlldb/unittests/Symbol/Inputs/inlined-functions.yaml
The file was modifiedllvm/test/ObjectYAML/MachO/DWARF5-debug_info.yaml
The file was modifiedllvm/test/tools/llvm-gsymutil/X86/mach-dwarf.yaml
The file was modifiedllvm/test/ObjectYAML/MachO/DWARF-debug_info.yaml
The file was modifiedllvm/test/tools/llvm-dwarfdump/X86/verify_attr_file_indexes_no_files.yaml
The file was modifiedllvm/test/tools/llvm-gsymutil/ARM_AArch64/fat-macho-dwarf.yaml
The file was modifiedllvm/lib/ObjectYAML/DWARFYAML.cpp
The file was modifiedllvm/test/tools/yaml2obj/ELF/DWARF/debug-line.yaml
The file was modifiedllvm/test/tools/llvm-dwarfdump/X86/verify_attr_file_indexes.yaml
Commit 22b615a96593f13109a27cabfd1764ec4f558c7a by daniel.kiss
[libunwind] Support for leaf function unwinding.

Unwinding leaf function is useful in cases when the backtrace finds a
leaf function for example when it caused a signal.
This patch also add the support for the DW_CFA_undefined because it marks
the end of the frames.

Ryan Prichard provided code for the tests.

Reviewed By: #libunwind, mstorsjo

Differential Revision: https://reviews.llvm.org/D83573

Reland with limit the test to the x86_64-linux target.
The file was modifiedlibunwind/src/DwarfParser.hpp
The file was addedlibunwind/test/signal_unwind.pass.cpp
The file was addedlibunwind/test/unwind_leaffunction.pass.cpp
The file was modifiedlibunwind/src/DwarfInstructions.hpp
The file was modifiedlibunwind/test/lit.site.cfg.in
Commit 6690de098e43ac5741297e435aece71b971b5bd2 by spatel
[InstSimplify] add another test for NaN propagation; NFC
The file was modifiedllvm/test/Transforms/InstSimplify/ConstProp/cast.ll
Commit ae36c02ad0cb0a618c8715404dcfab4cf49c6612 by Mirko.Brkusanin
[AMDGPU] Set DS alignment requirements to be more strict

Alignment requirements for ds_read/write_b96/b128 for gfx9 and onward are
now the same as for other GCN subtargets. This way we can avoid any
unintentional use of these instructions on systems that do not support dword
alignment and instead require natural alignment.
This also makes 'SH_MEM_CONFIG.alignment_mode == STRICT' the default.

Differential Revision: https://reviews.llvm.org/D87821
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/ds_write2.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/store-local.128.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/store-local.96.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/store-local.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/ds_read2.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/load-local.128.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/lds-misaligned-bug.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/store-local.128.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/lds-misaligned-bug.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/load-local.128.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/load-local.96.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/load-local.96.ll
Commit 455ca0ebb69210046928fedffe292420a30f89ad by a.bataev
[SLP] Allow reordering of vectorization trees with reused instructions.

If some leaves have the same instructions to be vectorized, we may
incorrectly evaluate the best order for the root node (it is built for the
vector of instructions without repeated instructions and, thus, has less
elements than the root node). In this case we just can not try to reorder
the tree + we may calculate the wrong number of nodes that requre the
same reordering.
For example, if the root node is \<a+b, a+c, a+d, f+e\>, then the leaves
are \<a, a, a, f\> and \<b, c, d, e\>. When we try to vectorize the first
leaf, it will be shrink to \<a, b\>. If instructions in this leaf should
be reordered, the best order will be \<1, 0\>. We need to extend this
order for the root node. For the root node this order should look like
\<3, 0, 1, 2\>. This patch allows extension of the orders of the nodes
with the reused instructions.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D45263
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/vectorize-reorder-reuse.ll
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/jumbled_store_crash.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/reorder_repeated_ops.ll
Commit 27df1652709ba83d6b07f313297e7c796e36dce1 by Matthew.Arsenault
Revert "[amdgpu] Lower SGPR-to-VGPR copy in the final phase of ISel."

This reverts commit c3492a1aa1b98c8d81b0969d52cea7681f0624c2.

I think this is the wrong strategy and wrong place to do this
transform anyway. Also reverts follow up commit
7d593d0d6905b55ca1124fca5e4d1ebb17203138.
The file was modifiedllvm/lib/Target/AMDGPU/SIFoldOperands.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/wqm.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/waitcnt-vscnt.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/fabs.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/fneg-fabs.ll
The file was removedllvm/test/CodeGen/AMDGPU/sgpr-copy-cse.ll
Commit 05c02eda4552076dc08ce34866b3d8ee33bbf842 by Matthew.Arsenault
emacs: Add nofree and willreturn to list of attributes
The file was modifiedllvm/utils/emacs/llvm-mode.el
Commit 751a6c5760b8de591cf241effbdad1b1cae67814 by Matthew.Arsenault
IR: Move denormal mode parsing from MachineFunction to Function

This was just inspecting the IR to begin with, and is useful to check
in some places in the IR.
The file was modifiedllvm/include/llvm/IR/Function.h
The file was modifiedllvm/lib/CodeGen/MachineFunction.cpp
The file was modifiedllvm/lib/IR/Function.cpp
Commit 3f100e64b429b6468e9a2c5b3e7ef7757a06dc48 by spatel
[InstSimplify] fix fmin/fmax miscompile for partial undef vectors (PR47567)

It would also be correct to return the variable operand in these cases,
but eliminating a variable use is probably better for optimization.
The file was modifiedllvm/test/Transforms/InstSimplify/fminmax-folds.ll
The file was modifiedllvm/lib/Analysis/InstructionSimplify.cpp
Commit 1909b6ac0dbc2f1306103a5ea7f5e59f2232b133 by hanchung
[mlir][StandardToSPIRV] Handle vector of i1 case for lowering zexti to SPIR-V.

Reviewed By: mravishankar

Differential Revision: https://reviews.llvm.org/D87887
The file was modifiedmlir/test/Conversion/StandardToSPIRV/std-ops-to-spirv.mlir
The file was modifiedmlir/lib/Conversion/StandardToSPIRV/ConvertStandardToSPIRV.cpp
Commit c894bfd1f580e5807fc98cc353b0834e0c5ddc21 by adamcz
[clangd] Add option for disabling AddUsing tweak on some namespaces.

For style guides forbid "using" declarations for namespaces like "std".
With this new config option, AddUsing can be selectively disabled on
those.

Differential Revision: https://reviews.llvm.org/D87775
The file was modifiedclang-tools-extra/clangd/refactor/tweaks/AddUsing.cpp
The file was modifiedclang-tools-extra/clangd/ConfigCompile.cpp
The file was modifiedclang-tools-extra/clangd/ConfigFragment.h
The file was modifiedclang-tools-extra/clangd/Config.h
The file was modifiedclang-tools-extra/clangd/ConfigYAML.cpp
The file was modifiedclang-tools-extra/clangd/unittests/TweakTests.cpp
Commit 5d1f8395be94bdf6915ebeb4e51a4290c9497165 by daltenty
[AIX] Enable large code model when building with clang
The file was modifiedllvm/cmake/modules/HandleLLVMOptions.cmake
Commit d967aaa8fa801e2ed355058db98fd43e4b05edb6 by llvm-dev
[DAG] BuildVectorSDNode::getSplatValue - pull out repeated getNumOperands() calls. NFCI.
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Commit 81dce71acfaccbeea5dfc28c4bc0431952d8d9ca by llvm-dev
[X86][AVX] Add missing i686 broadcastm test coverage
The file was modifiedllvm/test/CodeGen/X86/broadcastm-lowering.ll
Commit 22dde1f92f68b4249dbae30c119972a17753236a by clementval
[mlir][openacc] Support Index and AnyInteger in loop op

Following patch D87712, this patch switch AnyInteger for operands gangNum, gangStatic,
workerNum, vectoreLength and tileOperands to Index and AnyInteger.

Reviewed By: ftynse

Differential Revision: https://reviews.llvm.org/D87848
The file was modifiedmlir/test/Dialect/OpenACC/ops.mlir
The file was modifiedmlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
The file was modifiedmlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
Commit 88a1d402d6c60aa182b9d83d39c9e3ab46a830c0 by clementval
[mlir][openacc] Add missing operands for acc.data operation

Add missing operands to represent copyin with readonly modifier, copyout with zero modifier
and create with zero modifier.

Reviewed By: ftynse

Differential Revision: https://reviews.llvm.org/D87874
The file was modifiedmlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
The file was modifiedmlir/test/Dialect/OpenACC/ops.mlir
The file was modifiedmlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
Commit 7b61b192753360427fade9c9c5b68cd76adfc665 by antiagainst
[MLIR][SPIRV] Create new ctx for deserialization in roundtrips.

Roundtripping SPIR-V modules used the same MLIRContext object for both
ways of the trip. This resulted in deserialization using a context
object already containing Types constructed during serialization.
This commit rectifies that by creating a new MLIRContext during
deserialization.

Reviewed By: mravishankar, antiagainst

Differential Revision: https://reviews.llvm.org/D87692
The file was modifiedmlir/lib/Dialect/SPIRV/Serialization/TranslateRegistration.cpp
Commit 23bab1eb43d39e7163eb55bcca6e412f68f930e3 by mascasa
[DFSan] Add strpbrk wrapper.

Reviewed By: vitalybuka

Differential Revision: https://reviews.llvm.org/D87849
The file was modifiedcompiler-rt/lib/dfsan/dfsan_custom.cpp
The file was modifiedcompiler-rt/test/dfsan/custom.cpp
The file was modifiedcompiler-rt/lib/dfsan/done_abilist.txt
Commit ceadd98c2fd51ab1faa80d142b2a6e080117e5ae by llvm-dev
[X86][AVX] lowerBuildVectorAsBroadcast - improve i64 BROADCASTM lowering on 32-bit targets

We already handle the the cases where we have a 'zero extended splat' build vector (a, 0, 0, 0, a, 0, 0, 0, ...) but were missing the case where the 'a' scalar was zero-extended as well - such as i64 -> vXi64 splat cases on 32-bit targets.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/broadcastm-lowering.ll
The file was modifiedllvm/test/CodeGen/X86/avx512cd-intrinsics-fast-isel.ll
The file was modifiedllvm/test/CodeGen/X86/avx512vlcd-intrinsics-fast-isel.ll
Commit 3c2e2df8d03e8ac8e7be1733950993090f2b4710 by lyandy
[MLIR][ODS] Add constBuilderCall for TypeArrayAttr

constBuilderCall was not defined for TypeArrayAttr, resulting in tblgen not emitting the correct code when TypeArrayAttr is used with a default valued attribute.

Reviewed By: antiagainst

Differential Revision: https://reviews.llvm.org/D87907
The file was modifiedmlir/include/mlir/IR/OpBase.td
The file was modifiedmlir/test/lib/Dialect/Test/TestOps.td
Commit 51c5add8547a66caa5fbc9a19a91cd7976944229 by jonathan_roelofs
Extending Baremetal toolchain's support for the rtlib option.

Differential Revision: https://reviews.llvm.org/D87164

Patch by Manuel Carrasco!
The file was modifiedclang/test/Driver/baremetal.cpp
The file was modifiedclang/lib/Driver/ToolChains/BareMetal.cpp
Commit cab6f5b2ab814a4be3fd71aacdbe10298f512833 by jianzhouzh
Use one more byte to silence a warning from Vistual C++
The file was modifiedllvm/include/llvm/Bitstream/BitstreamWriter.h
Commit 0345d88de654259ae90494bf9b015416e2cccacb by francisvm
[NFC][ScheduleDAG] Remove unused EntrySU SUnit

EntrySU doesn't seem to be used at all when building the ScheduleDAG.

Differential Revision: https://reviews.llvm.org/D87867
The file was modifiedllvm/lib/CodeGen/ScheduleDAG.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/ScheduleDAGVLIW.cpp
The file was modifiedllvm/include/llvm/CodeGen/MachineScheduler.h
The file was modifiedllvm/include/llvm/CodeGen/ScheduleDAG.h
The file was modifiedllvm/lib/CodeGen/MachineScheduler.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIMachineScheduler.h
The file was modifiedllvm/lib/CodeGen/ScheduleDAGInstrs.cpp
The file was modifiedllvm/lib/CodeGen/PostRASchedulerList.cpp
The file was modifiedllvm/lib/CodeGen/MacroFusion.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
The file was modifiedllvm/lib/Target/AMDGPU/GCNMinRegStrategy.cpp
Commit a9be2b5cb2b3e752c6de2fab24aa5ad94500802b by jonchesterfield
[libomptarget] Disable build of amdgpu plugin as it doesn't build with rocm.
The file was modifiedopenmp/libomptarget/plugins/CMakeLists.txt
Commit 2e7add812eb7bdd90bd0f0fc3b633515edd55f27 by mydeveloperday
[clang-format] Add a option for the position of Java static import

Some Java style guides and IDEs group Java static imports after
non-static imports. This patch allows clang-format to control
the location of static imports.

Patch by: @bc-lee

Reviewed By: MyDeveloperDay, JakeMerdichAMD

Differential Revision: https://reviews.llvm.org/D87201
The file was modifiedclang/docs/ClangFormatStyleOptions.rst
The file was modifiedclang/lib/Format/Format.cpp
The file was modifiedclang/unittests/Format/FormatTest.cpp
The file was modifiedclang/unittests/Format/SortImportsTestJava.cpp
The file was modifiedclang/include/clang/Format/Format.h
Commit a16e4a63ae7c1933291577723324e412e087dc8e by mydeveloperday
[clang-format] NFC ensure the clang-format tests remain clang-formatted
The file was modifiedclang/unittests/Format/FormatTestCSharp.cpp
Commit 7c44651360dd94e17011fd1cd7ec3c755e0363b4 by silvasean
[mlir][shape] Extend shape.cstr_require with a message.

I realized when using this that one can't get very good error messages
without an additional message attribute.

Differential Revision: https://reviews.llvm.org/D87875
The file was modifiedmlir/include/mlir/Dialect/Shape/IR/ShapeOps.td
The file was modifiedmlir/test/Dialect/Shape/canonicalize.mlir
The file was modifiedmlir/test/Dialect/Shape/ops.mlir
Commit 9b6765e784b39c88cb8cdb85ab083e6c95a997ed by usx
[clangd] Add Random Forest runtime for code completion.

Summary:
[WIP]
- Proposes a json format for representing Random Forest model.
- Proposes a way to test the generated runtime using a test model.

TODO:
- Add generated source code snippet for easier review.
- Fix unused label warning.
- Figure out required using declarations for CATEGORICAL columns from Features.json.
- Necessary Google3 internal modifications for blaze before landing.
- Add documentation for format of the model.
- Document more.

Subscribers: mgorny, ilya-biryukov, MaskRay, jkorous, arphaman, kadircet, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D83814
The file was modifiedclang-tools-extra/clangd/CMakeLists.txt
The file was addedclang-tools-extra/clangd/quality/model/features.json
The file was addedclang-tools-extra/clangd/quality/README.md
The file was addedclang-tools-extra/clangd/unittests/DecisionForestTests.cpp
The file was addedclang-tools-extra/clangd/quality/CompletionModelCodegen.py
The file was addedclang-tools-extra/clangd/quality/model/forest.json
The file was addedclang-tools-extra/clangd/unittests/decision_forest_model/forest.json
The file was addedclang-tools-extra/clangd/quality/CompletionModel.cmake
The file was addedclang-tools-extra/clangd/unittests/decision_forest_model/CategoricalFeature.h
The file was modifiedclang-tools-extra/clangd/unittests/CMakeLists.txt
The file was modifiedclang-tools-extra/clangd/unittests/CodeCompleteTests.cpp
The file was addedclang-tools-extra/clangd/unittests/decision_forest_model/features.json
Commit 615695de27e417d6b444cd983e6f636373afc8c9 by Amara Emerson
[AArch64][GlobalISel] Make <8 x s8> of G_BUILD_VECTOR legal.
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-build-vector.mir
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
Commit 0576f436e577cede25810729aef236ec8c649446 by Matthew.Arsenault
AMDGPU: Don't sometimes allow instructions before lowered si_end_cf

Since 6524a7a2b9ca072bd7f7b4355d1230e70c679d2f, this would sometimes
not emit the or to exec at the beginning of the block, where it really
has to be. If there is an instruction that defines one of the source
operands, split the block and turn the si_end_cf into a terminator.

This avoids regressions when regalloc fast is switched to inserting
reloads at the beginning of the block, instead of spills at the end of
the block.

In a future change, this should always split the block.
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/si-lower-control-flow.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIInstructions.td
The file was modifiedllvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/lower-control-flow-other-terminators.mir
The file was modifiedllvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
Commit 01def7f7c3f1f762ce57a89aceb85214669911c3 by pklausler
[flang] Rework preprocessing of stringification

Hew more closely to the C17 standard; perform macro replacement
of arguments to function-like macros unless they're being stringified
or pasted.  Test with a model "assert" macro idiom that exposed
the problem.

Differential Revision: https://reviews.llvm.org/D87650
The file was modifiedflang/lib/Parser/parsing.cpp
The file was addedflang/test/Preprocessing/assert.F90
The file was modifiedflang/lib/Parser/preprocessor.cpp
The file was modifiedflang/lib/Parser/preprocessor.h
The file was modifiedflang/lib/Parser/prescan.cpp
The file was modifiedflang/lib/Parser/prescan.h
Commit 06fe76cc4f5972b04dd4ad7b9dcb4425a73dccba by aeubanks
[ASan][NewPM] Fix byref-args.ll under NPM
The file was modifiedllvm/test/Instrumentation/AddressSanitizer/byref-args.ll
Commit a1aa330b202f97ecd243ea9ef0c7ac00a80ea653 by raul.tambre
[Sema] Handle objc_super special lookup when checking builtin compatibility

objc_super is special and needs LookupPredefedObjCSuperType() called before performing builtin type comparisons.
This fixes an error when compiling macOS headers. A test is added.

Differential Revision: https://reviews.llvm.org/D87917
The file was addedclang/test/SemaObjCXX/builtin-objcsuper.mm
The file was modifiedclang/lib/Sema/SemaDecl.cpp
Commit e0802fe0162fcab12de5f134dc0848a8e4dfbc92 by dblaikie
DebugInfo: Tidy up initializing multi-section contributions in DWARFContext
The file was modifiedllvm/lib/DebugInfo/DWARF/DWARFContext.cpp
Commit d419e34c4d7e9e0b2b3f99b77246e57a03b2459b by aeubanks
[test][HWAsan] Fix kernel-inline.ll under NPM
The file was modifiedllvm/test/Instrumentation/HWAddressSanitizer/kernel-inline.ll
Commit 91aed9bf975f1e4346cc8f4bdefc98436386ced2 by zequanwu
[CodeGen] emit CG profile for COFF object file

I forgot to add emission of CG profile for COFF object file, when adding the support (https://reviews.llvm.org/D81775)

Differential Revision: https://reviews.llvm.org/D87811
The file was modifiedllvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
The file was modifiedllvm/include/llvm/Target/TargetLoweringObjectFile.h
The file was modifiedllvm/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h
The file was modifiedllvm/lib/Target/TargetLoweringObjectFile.cpp
The file was addedllvm/test/MC/COFF/cgprofile.ll
Commit 870fd53e4f6357946f4bad0b861c510cd107420c by Matthew.Arsenault
Reapply "RegAllocFast: Record internal state based on register units"

The regressions this caused should be fixed when
https://reviews.llvm.org/D52010 is applied.

This reverts commit a21387c65470417c58021f8d3194a4510bb64f46.
The file was modifiedllvm/test/DebugInfo/X86/op_deref.ll
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The file was modifiedllvm/test/CodeGen/AArch64/fast-isel-sp-adjust.ll
The file was modifiedllvm/test/CodeGen/X86/pr1489.ll
The file was modifiedllvm/test/CodeGen/PowerPC/addegluecrash.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/indirect-addressing-term.ll
The file was modifiedllvm/test/CodeGen/PowerPC/popcount.ll
The file was modifiedllvm/test/CodeGen/X86/crash-O0.ll
The file was modifiedllvm/test/CodeGen/X86/swift-return.ll
The file was modifiedllvm/test/CodeGen/Mips/atomic-min-max.ll
The file was modifiedllvm/lib/CodeGen/RegAllocFast.cpp
The file was modifiedllvm/test/CodeGen/X86/atomic-unordered.ll
The file was modifiedllvm/test/CodeGen/SPARC/fp16-promote.ll
The file was modifiedllvm/test/CodeGen/X86/pr30813.ll
The file was modifiedllvm/test/CodeGen/X86/pr32284.ll
The file was modifiedllvm/test/CodeGen/AArch64/popcount.ll
The file was modifiedllvm/test/CodeGen/X86/avx-load-store.ll
The file was modifiedllvm/test/CodeGen/X86/avx512-mask-zext-bugfix.ll
The file was modifiedllvm/test/CodeGen/X86/fast-isel-nontemporal.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-fast-isel-conversion-fallback.ll
The file was modifiedllvm/test/CodeGen/X86/pr39733.ll
The file was modifiedllvm/test/CodeGen/X86/2009-04-14-IllegalRegs.ll
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The file was modifiedllvm/test/CodeGen/PowerPC/vsx.ll
The file was modifiedllvm/test/CodeGen/Mips/implicit-sret.ll
The file was modifiedllvm/test/CodeGen/X86/extend-set-cc-uses-dbg.ll
The file was modifiedllvm/test/CodeGen/X86/atomic64.ll
The file was modifiedllvm/test/CodeGen/X86/lvi-hardening-loads.ll
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The file was modifiedllvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll
The file was modifiedllvm/test/CodeGen/X86/regalloc-fast-missing-live-out-spill.mir
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The file was modifiedllvm/test/CodeGen/X86/pr32241.ll
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The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fptosi_and_fptoui.ll
Commit c8757ff3aa7dd7a25a6343f6ef74a70c7be04325 by Matthew.Arsenault
RegAllocFast: Rewrite and improve

This rewrites big parts of the fast register allocator. The basic
strategy of doing block-local allocation hasn't changed but I tweaked
several details:

Track register state on register units instead of physical
registers. This simplifies and speeds up handling of register aliases.
Process basic blocks in reverse order: Definitions are known to end
register livetimes when walking backwards (contrary when walking
forward then uses may or may not be a kill so we need heuristics).

Check register mask operands (calls) instead of conservatively
assuming everything is clobbered.  Enhance heuristics to detect
killing uses: In case of a small number of defs/uses check if they are
all in the same basic block and if so the last one is a killing use.
Enhance heuristic for copy-coalescing through hinting: We check the
first k defs of a register for COPYs rather than relying on there just
being a single definition.  When testing this on the full llvm
test-suite including SPEC externals I measured:

average 5.1% reduction in code size for X86, 4.9% reduction in code on
aarch64. (ranging between 0% and 20% depending on the test) 0.5%
faster compiletime (some analysis suggests the pass is slightly slower
than before, but we more than make up for it because later passes are
faster with the reduced instruction count)

Also adds a few testcases that were broken without this patch, in
particular bug 47278.

Patch mostly by Matthias Braun
The file was modifiedllvm/test/CodeGen/AArch64/swift-return.ll
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The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/aggregate_struct_return.ll
The file was addedllvm/test/CodeGen/PowerPC/spill-nor0.mir
The file was modifiedllvm/test/CodeGen/X86/volatile.ll
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The file was modifiedllvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll
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The file was modifiedllvm/test/DebugInfo/X86/prologue-stack.ll
The file was modifiedllvm/test/DebugInfo/AArch64/frameindices.ll
The file was modifiedllvm/lib/CodeGen/RegAllocFast.cpp
The file was modifiedllvm/test/DebugInfo/X86/op_deref.ll
The file was modifiedllvm/test/CodeGen/Mips/implicit-sret.ll
The file was addedllvm/test/CodeGen/AMDGPU/fast-ra-kills-vcc.mir
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/load_split_because_of_memsize_or_align.ll
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The file was modifiedllvm/test/CodeGen/SystemZ/swift-return.ll
The file was modifiedllvm/test/CodeGen/X86/atomic32.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll
The file was modifiedllvm/test/CodeGen/PowerPC/aix-overflow-toc.py
The file was modifiedllvm/test/CodeGen/X86/pr32451.ll
The file was modifiedllvm/test/CodeGen/AArch64/combine-loads.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/reserve-vgpr-for-sgpr-spill.ll
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The file was modifiedllvm/test/CodeGen/X86/mixed-ptr-sizes.ll
The file was modifiedllvm/test/CodeGen/ARM/crash-greedy-v6.ll
The file was modifiedllvm/test/CodeGen/X86/stack-protector-strong-macho-win32-xor.ll
The file was modifiedllvm/test/CodeGen/X86/atomic6432.ll
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The file was addedllvm/test/CodeGen/X86/bug47278-eflags-error.mir
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Commit 3105d0f84bfa6b765bb88cbf090f557e588764ea by Matthew.Arsenault
CodeGen: Move split block utility to MachineBasicBlock

AMDGPU needs this in several places, so consolidate them here.
The file was modifiedllvm/lib/CodeGen/MachineBasicBlock.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
The file was modifiedllvm/include/llvm/CodeGen/MachineBasicBlock.h
The file was modifiedllvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
Commit ecba9d793e205ac857196abbd00cd67777e6f51a by llvm-dev
[X86][AVX] Add missing non AVX512VL broadcastm test coverage
The file was modifiedllvm/test/CodeGen/X86/broadcastm-lowering.ll
Commit f7a53d82c0902147909f28a9295a9d00b4b27d38 by jyknight
PR47468: Fix findPHICopyInsertPoint, so that copies aren't incorrectly inserted after an INLINEASM_BR.

findPHICopyInsertPoint special cases placement in a block with a
callbr or invoke in it. In that case, we must ensure that the copy is
placed before the INLINEASM_BR or call instruction, if the register is
defined prior to that instruction, because it may jump out of the
block.

Previously, the code placed it immediately after the last def _or
use_. This is wrong, if the use is the instruction which may jump.  We
could correctly place it immediately after the last def (ignoring
uses), but that is non-optimal for register pressure.

Instead, place the copy after the last def, or before the
call/inlineasm_br, whichever is later.

Differential Revision: https://reviews.llvm.org/D87865
The file was modifiedllvm/lib/CodeGen/PHIEliminationUtils.cpp
The file was addedllvm/test/CodeGen/X86/callbr-asm-phi-placement.ll
Commit 51a505340dfdfdfd9ab32c7267a74db3cdeefa56 by dblaikie
DebugInfo: Simplify line table parsing to take all the units together, rather than CUs and TUs separately
The file was modifiedllvm/unittests/DebugInfo/DWARF/DWARFDebugLineTest.cpp
The file was modifiedllvm/include/llvm/DebugInfo/DWARF/DWARFDebugLine.h
The file was modifiedllvm/lib/DebugInfo/DWARF/DWARFDebugLine.cpp
The file was modifiedllvm/lib/DebugInfo/DWARF/DWARFContext.cpp
Commit 82af17cde8caa8d2d020237f644d4302fc4fa589 by dblaikie
Linewrap & remove some dead typedefs from previous commit

Cleanup for 51a505340dfdfdfd9ab32c7267a74db3cdeefa56
The file was modifiedllvm/include/llvm/DebugInfo/DWARF/DWARFDebugLine.h
Commit 9ad6049736c58cca098b13ed128e7de0940f94a0 by huihuiz
[InstCombine][SVE] Skip scalable type for InstCombiner::getFlippedStrictnessPredicateAndConstant.

We cannot iterate on scalable vector, the number of elements is unknown at compile-time.

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D87918
The file was addedllvm/test/Transforms/InstCombine/vscale_cmp.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
Commit 2b1cb6d54a3298204e01a2982e3d00a1f08743a2 by aeubanks
[test][TSan] Fix tests under NPM

Under NPM, the TSan passes are split into a module and function pass. A
couple tests were testing for inserted module constructors, which is
only part of the module pass.
The file was modifiedllvm/test/Instrumentation/ThreadSanitizer/do-not-instrument-memory-access.ll
The file was modifiedllvm/test/Instrumentation/ThreadSanitizer/tsan_basic.ll
Commit 4ebd30722af5175282b99938d163ad4459aa5968 by llvm-dev
[X86][AVX] lowerBuildVectorAsBroadcast - improve BROADCASTM lowering on non-VLX targets

Broadcast to a ZMM type then extract the low subvector.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/broadcastm-lowering.ll
Commit 7bd75b630144ec639dbbf7bcb2797f48380b953b by peter
scudo: Add an API for disabling memory initialization per-thread.

Here "memory initialization" refers to zero- or pattern-init on
non-MTE hardware, or (where possible to avoid) memory tagging on MTE
hardware. With shared TSD the per-thread memory initialization state
is stored in bit 0 of the TLS slot, similar to PointerIntPair in LLVM.

Differential Revision: https://reviews.llvm.org/D87739
The file was modifiedcompiler-rt/lib/scudo/standalone/common.h
The file was modifiedcompiler-rt/lib/scudo/standalone/tests/combined_test.cpp
The file was modifiedcompiler-rt/lib/scudo/standalone/combined.h
The file was modifiedcompiler-rt/lib/scudo/standalone/tsd_exclusive.h
The file was modifiedcompiler-rt/lib/scudo/standalone/wrappers_c.inc
The file was modifiedcompiler-rt/lib/scudo/standalone/tsd_shared.h
The file was modifiedcompiler-rt/lib/scudo/standalone/tests/chunk_test.cpp
The file was modifiedcompiler-rt/lib/scudo/standalone/chunk.h
The file was modifiedcompiler-rt/lib/scudo/standalone/include/scudo/interface.h
Commit 85185b61b6371c29111611b8e3ac8d06403542c8 by stellaraccident
First pass on MLIR python context lifetime management.

* Per thread https://llvm.discourse.group/t/revisiting-ownership-and-lifetime-in-the-python-bindings/1769
* Reworks contexts so it is always possible to get back to a py::object that holds the reference count for an arbitrary MlirContext.
* Retrofits some of the base classes to automatically take a reference to the context, elimintating keep_alives.
* More needs to be done, as discussed, when moving on to the operations/blocks/regions.

Differential Revision: https://reviews.llvm.org/D87886
The file was modifiedmlir/lib/Bindings/Python/IRModules.cpp
The file was modifiedmlir/lib/Bindings/Python/IRModules.h
The file was modifiedmlir/lib/CAPI/IR/IR.cpp
The file was modifiedmlir/include/mlir-c/IR.h
The file was addedmlir/test/Bindings/Python/context_lifecycle.py
Commit 0ea2a57274225066ad81e971659222cf9ee1d12d by thakis
clangd:  Make ompletionModelCodegen.py tpy2.7 compatible

LLVM still supports Python 2.7, so unbreak bots that still run that.
In a separate commit so that this is easy to revert once we drop
support :)
The file was modifiedclang-tools-extra/clangd/quality/CompletionModelCodegen.py
Commit 442801a7b9b5460114498c48c12b8af40e495188 by thakis
[gn build] (manually) port 9b6765e784b3
The file was modifiedllvm/utils/gn/secondary/clang-tools-extra/clangd/BUILD.gn
Commit ae0ecb3c505e013659d9fa2668c55d93c1fff0b9 by kparzysz
Pre-commit test for CSEing masked loads/stores
The file was addedllvm/test/Transforms/EarlyCSE/masked-intrinsics-unequal-masks.ll
Commit 9b346f974ea606e17064969568568da30394c7a2 by thakis
[gn build] Do not sync filenames containing variable references
The file was modifiedllvm/utils/gn/build/sync_source_lists_from_cmake.py
Commit b168bbfae42e792542b4ced8729599524b9759c5 by vmiklos
[clang-format] Recognize "hxx" as a C++ header in clang-format-diff.py

And shift "proto" to the next line to avoid a too long line.

Reviewed By: MyDeveloperDay

Differential Revision: https://reviews.llvm.org/D87931
The file was modifiedclang/tools/clang-format/clang-format-diff.py
Commit ecfd8161bf43d035eafb75c14e9cf4a6d3966946 by echristo
Temporarily Revert "[SLP] Allow reordering of vectorization trees with reused instructions."
as it's infinite looping on occasion.

This reverts commit 455ca0ebb69210046928fedffe292420a30f89ad.
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/reorder_repeated_ops.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/vectorize-reorder-reuse.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/jumbled_store_crash.ll
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Commit 929d91a55616d4fcf4754044b063644807b87fbe by thakis
[gn build] (manually) port 9b6765e784b3 more
The file was modifiedllvm/utils/gn/secondary/clang-tools-extra/clangd/BUILD.gn
The file was modifiedllvm/utils/gn/secondary/clang-tools-extra/clangd/unittests/BUILD.gn
Commit 7c2d83347f4ea146af1aca72fe289294aaf212be by thakis
[gn build] add file i forgot to add in 929d91a55616
The file was addedllvm/utils/gn/secondary/clang-tools-extra/clangd/quality/gen_decision_forest.gni
Commit d3b0644e22a4ebe599d58d9d319d2403484fd88f by spatel
[InstSimplify] add tests for constant folding fmin/fmax with undef op; NFC
The file was modifiedllvm/test/Transforms/InstSimplify/ConstProp/fp-undef.ll
Commit 7502040ed25e713546e64fe54a30beb5cfd8d045 by thakis
clang: Make changes in 7c8bb409f31e py2.7-compatible
The file was modifiedllvm/utils/UpdateTestChecks/common.py
Commit 807777913e82bece68a2f929ae17bd0e9ba38ab0 by thakis
CompletionModelCodegen: Remove unused import

The unused import is 3.4+, so it also breaks py2.7 compat.
But this is easy to fix :)
The file was modifiedclang-tools-extra/clangd/quality/CompletionModelCodegen.py
Commit 1c4c21489f013d6a501a52e79a36df07d772d9b8 by jhuber6
[OpenMP] Initial Support for OpenMP Webpage Documentation

Summary:
Adding support for generated html documentation for OpenMP. Changing
Cmake files to build the documentation and adding the base templates for
future documentation to be added.

Reviewers: jdoerfert

Subscribers: aaron.ballman arphaman guansong mgorny openmp-commits sstefan1 yaxunl

Tags: #OpenMP

Differential Revision: https://reviews.llvm.org/D87797
The file was addedopenmp/docs/_templates/layout.html
The file was modifiedopenmp/docs/ReleaseNotes.rst
The file was addedopenmp/docs/index.rst
The file was addedopenmp/docs/_themes/llvm-theme/static/llvm-theme.css
The file was modifiedopenmp/CMakeLists.txt
The file was addedopenmp/docs/README.txt
The file was addedopenmp/docs/_themes/llvm-theme/static/contents.png
The file was addedopenmp/docs/_themes/llvm-theme/theme.conf
The file was addedopenmp/docs/_templates/indexsidebar.html
The file was addedopenmp/docs/conf.py
The file was addedopenmp/docs/_themes/llvm-theme/layout.html
The file was addedopenmp/docs/_themes/llvm-theme/static/navigation.png
The file was addedopenmp/docs/_themes/llvm-theme/static/logo.png
The file was addedopenmp/docs/CMakeLists.txt
Commit 516d7574320554022e56bbdfcddb269f87a1ba0f by Vitaly Buka
[msan][asan] Add runtime flag intercept_strcmp

Can be used to disable interceptor to workaround issues of
non-instrumented code.

Reviewed By: morehouse, eugenis

Differential Revision: https://reviews.llvm.org/D87897
The file was addedcompiler-rt/test/asan/TestCases/strcmp.c
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_common_interceptors.inc
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_flags.inc
The file was addedcompiler-rt/test/msan/strcmp.c
Commit 3c731ba5f1b604c873e96ac137bfea723690ba95 by Vedant Kumar
[llvm-cov] Allow commas in filenames passed to `-object` flag

Currently, -object takes a comma separated list of objects as an
argument, which prevents it working with path names that contain a
comma. Drop comma-separated support, which requires to set pass the
-object flag multiple times to set multiple objects.

Patch by Andrew Gallagher!

Differential Revision: https://reviews.llvm.org/D87003
The file was modifiedllvm/tools/llvm-cov/CodeCoverage.cpp
The file was addedllvm/test/tools/llvm-cov/comma-in-coverage-object-filename.test
Commit 9932561b4892b6e9bbb0c2369272dfff2305fdb9 by rnk
[COFF] Move per-global .drective emission from AsmPrinter to TLOFCOFF

This changes the order of output sections and the output assembly, but
is otherwise NFC.

It simplifies the TLOF interface by removing two COFF-only methods.
The file was modifiedllvm/test/CodeGen/X86/dllexport.ll
The file was modifiedllvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
The file was modifiedllvm/test/CodeGen/ARM/global-merge-dllexport.ll
The file was modifiedllvm/test/CodeGen/X86/dllexport-x86_64.ll
The file was modifiedllvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
The file was modifiedllvm/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h
The file was modifiedllvm/include/llvm/Target/TargetLoweringObjectFile.h
Commit 1f0b43638ed7366189fb7b609484bb3033e678d9 by antiagainst
[spirv] Move device info from resource limit into target env

Vendor/device information are not resource limits. Moving to
target environment directly for better organization.

Reviewed By: mravishankar

Differential Revision: https://reviews.llvm.org/D87911
The file was modifiedmlir/include/mlir/Dialect/SPIRV/SPIRVAttributes.h
The file was modifiedmlir/lib/Dialect/SPIRV/TargetAndABI.cpp
The file was modifiedmlir/test/Dialect/SPIRV/target-and-abi.mlir
The file was modifiedmlir/include/mlir/Dialect/SPIRV/TargetAndABI.td
The file was modifiedmlir/include/mlir/Dialect/SPIRV/SPIRVBase.td
The file was modifiedmlir/lib/Dialect/SPIRV/SPIRVDialect.cpp
The file was modifiedmlir/docs/Dialects/SPIR-V.md
The file was modifiedmlir/lib/Dialect/SPIRV/SPIRVAttributes.cpp
The file was modifiedmlir/include/mlir/Dialect/SPIRV/TargetAndABI.h
Commit 549e55b3d5634870aa9d42135f51ad46a6a0e347 by echristo
Temporarily Revert "[clangd] Add Random Forest runtime for code completion."
as a header doesn't appear to have made it into the commit.

This reverts commit 9b6765e784b39c88cb8cdb85ab083e6c95a997ed and followup
The file was removedclang-tools-extra/clangd/quality/CompletionModelCodegen.py
The file was removedclang-tools-extra/clangd/quality/model/features.json
The file was removedclang-tools-extra/clangd/quality/README.md
The file was removedclang-tools-extra/clangd/unittests/decision_forest_model/forest.json
The file was modifiedclang-tools-extra/clangd/unittests/CMakeLists.txt
The file was modifiedclang-tools-extra/clangd/CMakeLists.txt
The file was removedclang-tools-extra/clangd/unittests/decision_forest_model/features.json
The file was removedclang-tools-extra/clangd/unittests/DecisionForestTests.cpp
The file was removedclang-tools-extra/clangd/unittests/decision_forest_model/CategoricalFeature.h
The file was removedclang-tools-extra/clangd/quality/CompletionModel.cmake
The file was removedclang-tools-extra/clangd/quality/model/forest.json
The file was modifiedclang-tools-extra/clangd/unittests/CodeCompleteTests.cpp
Commit 7c10129f5a2145cf8f6dbe259269fd2a781a8dbe by aeubanks
[test][InstrProf] Fix always_inline.ll under NPM

NPM's inliner does not clean up dead functions.

Differential Revision: https://reviews.llvm.org/D87922
The file was modifiedllvm/test/Instrumentation/InstrProfiling/always_inline.ll
Commit 06f136f61e6d23fde5c91f7fa0813d0291c17c97 by listmail
[instcombine][x86] Converted pdep/pext with shifted mask to simple arithmetic

If the mask of a pdep or pext instruction is a shift masked (i.e. one contiguous block of ones) we need at most one and and one shift to represent the operation without the intrinsic. One all platforms I know of, this is faster than the pdep/pext.

The cost modelling for multiple contiguous blocks might be worth exploring in a follow up, but it's not relevant for my current use case. It would almost certainly be a win on AMDs where these are really really slow though.

Differential Revision: https://reviews.llvm.org/D87861
The file was modifiedllvm/lib/Target/X86/X86InstCombineIntrinsic.cpp
The file was modifiedllvm/test/Transforms/InstCombine/X86/x86-bmi-tbm.ll
Commit ed79827aea444e6995fb3d36abc2bfd36331773c by zixu_wang
[clang][module] Improve incomplete-umbrella warning

Change the warning message for -Wincomplete-umbrella to report the location of the umbrella header;

Differential Revision: https://reviews.llvm.org/D82118
The file was modifiedclang/test/Modules/incomplete-umbrella.m
The file was modifiedclang/lib/Lex/PPLexerChange.cpp
Commit b86f1af423952d9f1dbe105b651b948ce0e1e8d0 by snehasishk
[clang] Remove profile available check for fsplit-machine-functions.

Enforcing a profile available check in the driver does not work with
incremental LTO builds where the LTO backend invocation does not include
the profile flags. At this point the profiles have already been consumed
and the IR contains profile metadata. Instead we always pass through the
-fsplit-machine-functions flag on user request. The pass itself contains
a check to return early if no profile information is available.

Differential Revision: https://reviews.llvm.org/D87943
The file was modifiedclang/lib/Driver/ToolChains/Clang.cpp
The file was modifiedclang/test/Driver/fsplit-machine-functions.c
Commit 82827244e9bbc2804afd9070158c567ac89f0540 by Vitaly Buka
[NFC][sanitizer] Don't use ::testing::internal
The file was modifiedcompiler-rt/lib/sanitizer_common/tests/sanitizer_stackdepot_test.cpp
Commit 51b75b87dbbed24b9c0a809f7e4d22b31923630d by i
[lld][WebAssembly] Fix -Wunused-variable after D87663
The file was modifiedlld/wasm/Writer.cpp
Commit 37e7673c21af1531b601ca975cb6118d04b6e1cc by amy.kwan1
[PowerPC] Implement Move to VSR Mask builtins in LLVM/Clang

This patch implements the vec_gen[b|h|w|d|q]m function prototypes in altivec.h
in order to utilize the move to VSR with mask instructions introduced in Power10.

Differential Revision: https://reviews.llvm.org/D82725
The file was modifiedclang/test/CodeGen/builtins-ppc-p10vector.c
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrPrefix.td
The file was modifiedllvm/include/llvm/IR/IntrinsicsPowerPC.td
The file was modifiedclang/lib/Headers/altivec.h
The file was modifiedllvm/test/CodeGen/PowerPC/p10-vector-mask-ops.ll
The file was modifiedclang/include/clang/Basic/BuiltinsPPC.def
Commit 5d34d7f1a0cae8367066ce2b55afe42b94a7466f by Amara Emerson
[GlobalISel] Add lowering support for G_ABS and use for AArch64.

Differential Revision: https://reviews.llvm.org/D87952
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/legalize-abs.mir
The file was modifiedllvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
Commit 76eec6c95b14abd5b72a805ac2e9bb3d8480679b by i
[SCEV] Fix an unused variable in -DLLVM_ENABLE_ASSERTIONS=off build
The file was modifiedllvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
Commit 3ab118a57d3803f45e3fe95321654994f2c9e1a1 by Vitaly Buka
[NFC][Asan] Fix test broken by RegAllocFast

The test worked only because by coincidence register with pointer was
clobbered.
After D52010 value is still preserved.
The file was modifiedcompiler-rt/test/asan/TestCases/Linux/leak.cpp
Commit 97bfac076a068b658923aeba34d82df4ef097ba5 by Vitaly Buka
[NFC][StackSafety] Replace auto with type

Fixes static analyzer is warning.
The file was modifiedllvm/lib/Analysis/StackSafetyAnalysis.cpp
Commit 269bcc39ca87c90b2b02a1b5b46686ae1929db3d by Amara Emerson
[AArch64][GlobalISel] Legalize arithmetic ops for <4 x s16>
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-vabs.ll
Commit cce24bb38d97c352bf7ac40860f0ade33024735c by Amara Emerson
[AArch64][GlobalISel] Add tests for pre-existing selection support for <4 x s16> arithmetic/bitwise ops.
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/select-binop.mir
Commit 034781f7f33634918025206427e6ee912ef3985b by Vitaly Buka
[NFC][LSan] Add REQUIRES: linux

Additional registers scaning is only implemented for x86 linux.
The file was modifiedcompiler-rt/test/lsan/TestCases/use_registers_extra.cpp
Commit 2ac06241d277c969c0dee0f40fb4f00971a4d7f7 by i
[LiveDebugValues] Add `#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)` to suppress -Wunused-function
The file was modifiedllvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp