SuccessChanges

Summary

  1. clang-x86-ninja-win10 - delete folder if it exists (details)
Commit d8fcebd8ab9f93d4fb71c079c393dfba7ce7cc13 by kuhnel
clang-x86-ninja-win10 - delete folder if it exists
The file was modifiedbuildbot/google/docker/buildbot-windows10-vs2019/VERSION (diff)
The file was modifiedbuildbot/google/docker/buildbot-windows10-vs2019/run.ps1 (diff)
The file was modifiedbuildbot/google/terraform/main.tf (diff)

Summary

  1. [AArch64] Cortex-A55 scheduler model (details)
  2. [NFC][ARM] More tail predication tests. (details)
  3. [llvm-readelf/obj] - Stop printing invalid names for unnamed section symbols. (details)
  4. Do not dereference an array out of bound just to take its address (details)
  5. [ARM] Select f32 constants with vmov.f16 (details)
  6. [mlir][VectorOps] Loosen restrictions on vector.reduction types (details)
  7. Recommit "[SCEV] Look through single value PHIs." (details)
  8. [AST] Reduce the size of TemplateArgumentLocInfo. (details)
  9. Revert "[NFC][ScheduleDAG] Remove unused EntrySU SUnit" (details)
  10. Fix buildbot. (details)
  11. [MLIR] Fix typo and expand gpu.host_register description. (details)
  12. [SyntaxTree][NFC] follow naming convention + remove auto on empty vector declaration (details)
  13. [SVE] Use NEON for extract_vector_elt when the index is in range. (details)
  14. [SVE] Change definition of reduction ISD nodes to have an SVE vector result type. (details)
Commit 4b8ade837e36b7f0181ce86fc23f33851d0fdd35 by sjoerd.meijer
[AArch64] Cortex-A55 scheduler model

This is an initial commit adding the A55 model, but it isn't used/enabled yet.
We will follow up on this to improve the model, then flip the switch.

The optimisation guide describing Cortex-A55 micro-architecture in more detail
can be found here:

https://static.docs.arm.com/epm128372/20/arm_cortex_a55_software_optimization_guide_v2.pdf

Original patch by Javed Absar.

Differential Revision: https://reviews.llvm.org/D46884
The file was modifiedllvm/lib/Target/AArch64/AArch64.td
The file was addedllvm/lib/Target/AArch64/AArch64SchedA55.td
Commit 13c73632c7cfcc2c8e70c93781d8fb9872153ede by sam.parker
[NFC][ARM] More tail predication tests.

Add mir tests for use/def of P0.
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-in-vpt.mir
Commit 095f6fbbd7b61af205d761f6951a869ec4a61722 by grimar
[llvm-readelf/obj] - Stop printing invalid names for unnamed section symbols.

We have an issue with `ELFDumper<ELFT>::getSymbolSectionName`:
1) It is used deeply for both LLVM/GNU styles and might return LLVM-style only
   values to describe symbols: "Undefined", "Processor Specific", "Absolute", etc.

2) `getSymbolSectionName` is used by `getFullSymbolName` and these special values
   might appear instead of symbol names in many places.
   This occurs for unnamed section symbols currently.

This patch extracts the LLVM specific logic to `LLVMStyle<ELFT>::printSymbolSection`,
which seems to be the only place where we want to print the special values mentioned.
It also adds a meaningful new warning that is reported when we are unable to get
a section index for a section symbol.

Differential revision: https://reviews.llvm.org/D87764
The file was modifiedllvm/test/tools/llvm-readobj/ELF/mips-plt.test
The file was modifiedllvm/test/tools/llvm-readobj/ELF/symbol-shndx.test
The file was modifiedllvm/tools/llvm-readobj/ELFDumper.cpp
The file was modifiedllvm/test/tools/llvm-readobj/ELF/dyn-symbols.test
The file was modifiedllvm/test/tools/llvm-readobj/ELF/mips-got.test
The file was modifiedllvm/test/tools/llvm-readobj/ELF/hash-symbols.test
Commit 2a774411174466010c69a2460c81b8d0d4f7165f by sguelton
Do not dereference an array out of bound just to take its address

This is UB by the standard, and caught by the libstdc++ asserts

Differential Revision: https://reviews.llvm.org/D87892
The file was modifiedflang/lib/Parser/token-sequence.cpp
Commit f4c5cadbcbb41f13cff0905449cfff4aef6a083c by david.green
[ARM] Select f32 constants with vmov.f16

This adds lowering for f32 values using the vmov.f16, which zeroes the
top bits whilst setting the lower bits to a pattern. This range of
values does not often come up, except where a f16 constant value has
been converted to a f32.

Differential Revision: https://reviews.llvm.org/D87790
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
The file was modifiedllvm/lib/Target/ARM/ARMInstrVFP.td
The file was modifiedllvm/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h
The file was modifiedllvm/test/CodeGen/ARM/fp16-bitcast.ll
The file was modifiedllvm/test/CodeGen/ARM/cmse-clear-float-hard.ll
Commit 2d76274b99f2c09cdd94863d6e2e48a06f863f2a by benny.kra
[mlir][VectorOps] Loosen restrictions on vector.reduction types

LLVM can deal with any integer or float type, don't arbitrarily restrict
it to f32/f64/i32/i64.

Differential Revision: https://reviews.llvm.org/D88010
The file was modifiedmlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir
The file was modifiedmlir/lib/Dialect/Vector/VectorOps.cpp
The file was modifiedmlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
Commit 11dccf8d3aa5d55210f8b886fb21926c7a8353ca by flo
Recommit "[SCEV] Look through single value PHIs."

This commit was originally because it was suspected to cause a crash,
but a reproducer did not surface.

A crash that was exposed by this change was fixed in 1d8f2e52925b.

This reverts the revert commit 0581c0b0eeba03da590d1176a4580cf9b9e8d1e3.
The file was modifiedllvm/test/Transforms/LoopStrengthReduce/funclet.ll
The file was modifiedllvm/test/Analysis/ScalarEvolution/solve-quadratic-overflow.ll
The file was modifiedllvm/lib/Analysis/ScalarEvolution.cpp
The file was modifiedllvm/test/Analysis/ScalarEvolution/solve-quadratic-i1.ll
Commit af29591650c43bd3bdc380c9d47b8bfd0f1664a2 by hokein.wu
[AST] Reduce the size of TemplateArgumentLocInfo.

allocate the underlying data of Template kind separately, this would reduce AST
memory usage

- TemplateArgumentLocInfo 24 => 8 bytes
- TemplateArgumentLoc  48 => 32 bytes
- DynTypeNode 56 => 40 bytes

ASTContext::.getASTAllocatedMemory changes:
  SemaDecl.cpp 255.5 MB => 247.5MB
  SemaExpr.cpp 293.5 MB => 283.5MB

Differential Revision: https://reviews.llvm.org/D87080
The file was modifiedclang/lib/AST/TemplateBase.cpp
The file was modifiedclang/lib/Sema/SemaTemplate.cpp
The file was modifiedclang/include/clang/AST/TemplateBase.h
The file was modifiedclang/lib/AST/TypeLoc.cpp
The file was modifiedclang/include/clang/AST/Expr.h
The file was modifiedclang/lib/AST/ASTImporter.cpp
The file was modifiedclang/lib/Sema/SemaTemplateDeduction.cpp
The file was modifiedclang/lib/Sema/SemaTemplateInstantiateDecl.cpp
The file was modifiedclang/lib/Sema/SemaTemplateVariadic.cpp
The file was modifiedclang/lib/Sema/TreeTransform.h
The file was modifiedclang/lib/Serialization/ASTReader.cpp
Commit 17dc729bd42947b839c9717a2efa9e1e04248616 by pifon
Revert "[NFC][ScheduleDAG] Remove unused EntrySU SUnit"

This reverts commit 0345d88de654259ae90494bf9b015416e2cccacb.

Google internal backend uses EntrySU, we are looking into removing
dependency on it.

Differential Revision: https://reviews.llvm.org/D88018
The file was modifiedllvm/lib/Target/AMDGPU/GCNMinRegStrategy.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
The file was modifiedllvm/include/llvm/CodeGen/MachineScheduler.h
The file was modifiedllvm/lib/CodeGen/ScheduleDAG.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
The file was modifiedllvm/lib/CodeGen/MachineScheduler.cpp
The file was modifiedllvm/lib/CodeGen/MacroFusion.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/ScheduleDAGVLIW.cpp
The file was modifiedllvm/include/llvm/CodeGen/ScheduleDAG.h
The file was modifiedllvm/lib/CodeGen/PostRASchedulerList.cpp
The file was modifiedllvm/lib/CodeGen/ScheduleDAGInstrs.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIMachineScheduler.h
Commit 41a8bbad5e52a94a485c5bfe3d7871784fe6d8ed by hokein.wu
Fix buildbot.

TemplateArgumentLocInfo cannot result in a constant expression anymore
after D87080.
The file was modifiedclang/include/clang/AST/TemplateBase.h
Commit 9ba3b7449d30c7a7b9be77ef3ac4016ba263b619 by csigg
[MLIR] Fix typo and expand gpu.host_register description.

See comments in https://reviews.llvm.org/D85631.

Reviewed By: herhut

Differential Revision: https://reviews.llvm.org/D86214
The file was modifiedmlir/lib/Conversion/GPUCommon/ConvertLaunchFuncToRuntimeCalls.cpp
The file was modifiedmlir/include/mlir/Dialect/GPU/GPUOps.td
Commit 87f0b51d68de40e7106be89d934b5191d983e3d5 by ecaldas
[SyntaxTree][NFC] follow naming convention + remove auto on empty vector declaration

Differential Revision: https://reviews.llvm.org/D88004
The file was modifiedclang/lib/Tooling/Syntax/Nodes.cpp
The file was modifiedclang/lib/Tooling/Syntax/Tree.cpp
The file was modifiedclang/lib/Tooling/Syntax/BuildTree.cpp
Commit 6457455248d5b83a7e4274f06b6313b15cd51421 by paul.walker
[SVE] Use NEON for extract_vector_elt when the index is in range.

Patch also adds missing patterns for unpacked vector types and
extracts of element zero.

Differential Revision: https://reviews.llvm.org/D87842
The file was modifiedllvm/test/CodeGen/AArch64/sve-insert-element.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-extract-element.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
The file was modifiedllvm/test/CodeGen/AArch64/sve-split-extract-elt.ll
Commit f3fa954b5b19acdd4b95ff2ca1ff4f74f4b6b21b by paul.walker
[SVE] Change definition of reduction ISD nodes to have an SVE vector result type.

The current nodes, AArch64::SMAXV_PRED for example, are defined to
return a NEON vector result.  This is incorrect because they modify
the complete SVE register and are thus changed to represent such.

This patch also adds nodes for UADDV_PRED and SADDV_PRED, which
unifies the handling of all SVE reductions.

NOTE: Floating-point reductions are already implemented correctly,
so this patch is essentially making everything consistent with those.

Differential Revision: https://reviews.llvm.org/D87843
The file was modifiedllvm/lib/Target/AArch64/SVEInstrFormats.td
The file was modifiedllvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.h
The file was modifiedllvm/test/CodeGen/AArch64/sve-int-reduce-pred.ll