Commit
05290eead3f95e02700890321ccf6719770f91fe
by llvm-devInstCombine] collectBitParts - cleanup variable names. NFCI.
Fix a number of WShadow warnings (I was used as the instruction and index......) and fix cases to match style.
Also, replaced the Bit APInt mask check in AND instructions with a direct APInt[] bit check.
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 | llvm/lib/Transforms/Utils/Local.cpp |
Commit
413b4998bd722ab671e29e6dff5d458d1869f39b
by llvm-dev[InstCombine] recognizeBSwapOrBitReverseIdiom - use ArrayRef::back() helper. NFCI.
Post-commit feedback on D88316
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 | llvm/lib/Transforms/Utils/Local.cpp |
Commit
3f88c10a6b25668bb99f5eee7867dcbf37df973c
by sam.parker[RDA] isSafeToDefRegAt: Look at global uses
We weren't looking at global uses of a value, so we could happily overwrite the register incorrectly.
Differential Revision: https://reviews.llvm.org/D88554
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 | llvm/test/CodeGen/Thumb2/LowOverheadLoops/biquad-cascade-optsize-strd-lr.mir |
 | llvm/lib/CodeGen/ReachingDefAnalysis.cpp |
Commit
621c6c89627972d52796e64a9476a7d05f22f2cd
by llvm-dev[InstCombine] recognizeBSwapOrBitReverseIdiom - cleanup bswap/bitreverse detection loop. NFCI.
Early out if both pattern matches have failed (or we don't want them). Fix case of bit index iterator (and avoid Wshadow issue).
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 | llvm/lib/Transforms/Utils/Local.cpp |
Commit
08c5720405d5204ec2329b7f6c561062c7dddee2
by llvm-dev[InstCombine] Add PR47191 bswap tests
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 | llvm/test/Transforms/InstCombine/bswap.ll |
Commit
f794160c6cb7da4b5ef354a91fe498341f651d36
by emaste[lldb] Fix FreeBSD Arm Process Plugin build
Add a missing include and some definitions in 769533216666.
Patch by: Brooks Davis
Reviewed by: labath
Differential Revision: https://reviews.llvm.org/D88453
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 | lldb/source/Plugins/Process/FreeBSD/RegisterContextPOSIXProcessMonitor_arm.h |
 | lldb/source/Plugins/Process/FreeBSD/RegisterContextPOSIXProcessMonitor_arm.cpp |
Commit
d8563654701c79fb9ab28ecf94567d9934baed05
by flo[VPlan] Change recipes to inherit from VPUser instead of a member var.
Now that VPUser is not inheriting from VPValue, we can take the next step and turn the recipes that already manage their operands via VPUser into VPUsers directly. This is another small step towards traversing def-use chains in VPlan.
This is NFC with respect to the generated code, but makes the interface more powerful.
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 | llvm/unittests/Transforms/Vectorize/VPlanTest.cpp |
 | llvm/lib/Transforms/Vectorize/LoopVectorize.cpp |
 | llvm/lib/Transforms/Vectorize/VPlan.h |
 | llvm/lib/Transforms/Vectorize/VPlanValue.h |
Commit
762e8f9bbdaf43300dbc75637a8bce1ce643cc06
by mgorny[lldb] [Process/NetBSD] Fix operating on ftag register
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 | lldb/source/Plugins/Process/NetBSD/NativeRegisterContextNetBSD_x86_64.cpp |
Commit
d5545a8993489ee426b757482a64c9373cf7cf38
by llvm-dev[InstCombine] recognizeBSwapOrBitReverseIdiom - remove unnecessary cast. NFCI.
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 | llvm/lib/Transforms/Utils/Local.cpp |
Commit
7fcad5583a12026ce19afe487681753ac633064a
by llvm-dev[InstCombine] Remove %tmp variable names from bswap tests
Appease update_test_checks script that was complaining about potential %TMP clashes
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 | llvm/test/Transforms/InstCombine/bswap.ll |
Commit
c722b3259690d3aad20f31d0ffe6c12b1416bccc
by llvm-dev[InstCombine] recognizeBSwapOrBitReverseIdiom - merge the regular/trunc+zext paths. NFCI.
There doesn't seem to be any good reason for having a separate path for when we bswap/bitreverse at a smaller size than the destination size - so merge these to make the instruction generation a lot clearer.
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 | llvm/lib/Transforms/Utils/Local.cpp |
Commit
216af81c39d1cc4e90af7b991d517c4c7acc912e
by sam.mccall[clangd] Fix invalid UTF8 when extracting doc comments.
Differential Revision: https://reviews.llvm.org/D88567
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 | clang-tools-extra/clangd/unittests/CodeCompletionStringsTests.cpp |
 | clang-tools-extra/clangd/unittests/SymbolCollectorTests.cpp |
 | clang-tools-extra/clangd/CodeCompletionStrings.cpp |
Commit
dfb717da1f794c235b81a985a57dc238c82318e6
by sd.fertile[PowerPC] Remove support for VRSAVE save/restore/update.
After removal of Darwin as a PowerPC subtarget, the VRSAVE save/restore/spill/update code is no longer needed by any supported subtarget, so remove it while keeping support for vrsave and related instruction aliases for inline asm. I've pre-commited tests to document the existing vrsave handling in relation to @llvm.eh.unwind.init and inline asm usage, as well as a test which shows a beahviour change on AIX related to returning vector type as we were wrongly emiting VRSAVE_UPDATE on AIX.
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 | llvm/lib/Target/PowerPC/PPCInstrInfo.cpp |
 | llvm/test/CodeGen/PowerPC/aix-vector-return.ll |
 | llvm/lib/Target/PowerPC/PPCISelLowering.cpp |
 | llvm/lib/Target/PowerPC/PPCInstrInfo.h |
 | llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp |
 | llvm/lib/Target/PowerPC/PPCRegisterInfo.h |
 | llvm/lib/Target/PowerPC/PPCInstrInfo.td |
 | llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h |
 | llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp |
 | llvm/lib/Target/PowerPC/README_ALTIVEC.txt |
 | llvm/lib/Target/PowerPC/PPCFrameLowering.cpp |
Commit
43d239d0fadb1f8ea297580ca39dfbee96c913c1
by mikael.holmen[GlobalISel] Fix incorrect setting of ValNo when splitting
Before, for each original argument i, ValNo was set to i + PartIdx, but ValNo is intended to reflect the index of the value before splitting. Hence, ValNo should always be set to i and not consider the PartIdx.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D86511
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 | llvm/lib/CodeGen/GlobalISel/CallLowering.cpp |