SuccessChanges

Summary

  1. [clangd] Disable a failure TopLevelDecls test. (details)
  2. [lldb] Note difference in vFile:pread/pwrite format for lldb (details)
  3. [InstCombine] matchFunnelShift - canonicalize to OR(SHL,LSHR). NFCI. (details)
  4. [InstCombine] matchFunnelShift - remove shift value commutation. NFCI. (details)
  5. [InstCombine] matchFunnelShift - fold or(shl(a,x),lshr(b,sub(bw,x))) -> fshl(a,b,x) iff x < bw (REAPPLIED) (details)
  6. [AMDGPU] Use @LINE for error checking in gfx10 assembler tests (details)
  7. [SVE] Lower fixed length VECREDUCE_XOR operation (details)
  8. [AMDGPU] Insert waterfall loops for divergent calls (details)
  9. [LoopDeletion] Remove over-eager SCEV verification. (details)
  10. [AMDGPU] Print metadata on error (details)
  11. [NFC][Regalloc] Pass VirtRegMap by reference. (details)
  12. [VPlan] Use operands for printing of VPWidenMemoryInstructionRecipe. (details)
  13. [NFC][MC] Use MCRegister in LiveRangeMatrix (details)
  14. [Tests] Regenerate test checks; NFC (details)
Commit 16a4b0f0e36c8e1efa586ca4b2be8effefa75e6e by hokein.wu
[clangd] Disable a failure TopLevelDecls test.

The test fails on clang-ppc64le-rhel buildbot, needs further
investigation.
The file was modifiedclang-tools-extra/clangd/unittests/ParsedASTTests.cpp
Commit 2d1ee7cae9b2299186fa25d8d1fbdb8af482046c by david.spickett
[lldb] Note difference in vFile:pread/pwrite format for lldb

https://sourceware.org/gdb/current/onlinedocs/gdb/Host-I_002fO-Packets.html

States that all numbers should be hexidecimal but lldb
uses decimals in vFile:pread and vFile:pwrite.

lldb-server can accept either since it ends up using
strtoull which will detect the base being used.

Reviewed By: labath

Differential Revision: https://reviews.llvm.org/D89227
The file was modifiedlldb/docs/lldb-platform-packets.txt
Commit 02295e6d1a1559f0689aeca09d98f468e3f29d9a by llvm-dev
[InstCombine] matchFunnelShift - canonicalize to OR(SHL,LSHR). NFCI.

Simplify the shift amount matching code by canonicalizing the shift ops first.
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
Commit fa566233706ce8345f2c0152b51312a217b848c9 by llvm-dev
[InstCombine] matchFunnelShift - remove shift value commutation. NFCI.

After rG02295e6d1a15 we no longer need to invert the shift values for fshr - this is just hidden at the moment as funnel shifts only ever match for constant values so never use the fshr "Sub on SHL" path.
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
Commit bbf3925879b56aea42daeecc794bb41e99ebc126 by llvm-dev
[InstCombine] matchFunnelShift - fold or(shl(a,x),lshr(b,sub(bw,x))) -> fshl(a,b,x) iff x < bw (REAPPLIED)

If value tracking can confirm that a shift value is less than the type bitwidth then we can more confidently fold general or(shl(a,x),lshr(b,sub(bw,x))) patterns to a funnel/rotate intrinsic pattern without causing bad codegen regressions in the backend (see D89139).

Reapplied after the shift canonicalization in rG02295e6d1a15 which removed the need to flip the shift values.

Differential Revision: https://reviews.llvm.org/D88783
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
The file was modifiedllvm/test/Transforms/InstCombine/funnel.ll
The file was modifiedllvm/test/Transforms/InstCombine/rotate.ll
Commit b8901230c07eb363f8d61f71c436c36375b750db by jay.foad
[AMDGPU] Use @LINE for error checking in gfx10 assembler tests
The file was modifiedllvm/test/MC/AMDGPU/gfx10_unsupported.s
Commit 974ddb54c9adfb533f4bd9665ef902ebe75fa7ee by mcinally
[SVE] Lower fixed length VECREDUCE_XOR operation

Differential Revision: https://reviews.llvm.org/D88974
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/AArch64/sve-fixed-length-log-reduce.ll
Commit 7f2a641aad28fd9b15fa1bcae1dd496150638d79 by sebastian.neubauer
[AMDGPU] Insert waterfall loops for divergent calls

Extend loadSRsrcFromVGPR to allow moving a range of instructions into
the loop. The call instruction is surrounded by copies into physical
registers which should be part of the waterfall loop.

Differential Revision: https://reviews.llvm.org/D88291
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/indirect-call.ll
Commit ad5541045a63fe3049fc910d843bcbb78f7c7056 by flo
[LoopDeletion] Remove over-eager SCEV verification.

60b852092c98dbdc6248d60109d90ae6f8ad841c introduced SCEV verification to
deleteDeadLoop, but it appears this check is currently a bit over-eager
and some users of deleteDeadLoop appear to only patch up SE after
calling it (e.g. PR47753).

Remove the extra check for now. We can consider adding it back after we
tracked down the source of the inconsistency for PR47753.
The file was modifiedllvm/lib/Transforms/Utils/LoopUtils.cpp
Commit c2216d796aab7659771c05303f9d78bad4aeca07 by sebastian.neubauer
[AMDGPU] Print metadata on error

If the metadata is valid yaml, we can print it, even if it failed
validation. That makes it easier to debug any wrong metadata.

Differential Revision: https://reviews.llvm.org/D89243
The file was modifiedllvm/tools/llvm-readobj/ELFDumper.cpp
Commit 596a9f6b89d0d3e3f2897132ef1283941bd3607b by mtrofin
[NFC][Regalloc] Pass VirtRegMap by reference.

It's never null - the reason it's modeled as a pointer is because the
pass can't init it in its ctor. Passing by ref simplifies the code, too,
as the null checks were unnecessary complexity.

Differential Revision: https://reviews.llvm.org/D89171
The file was modifiedllvm/include/llvm/CodeGen/CalcSpillWeights.h
The file was modifiedllvm/lib/CodeGen/CalcSpillWeights.cpp
The file was modifiedllvm/lib/CodeGen/RegAllocBasic.cpp
The file was modifiedllvm/lib/CodeGen/RegAllocGreedy.cpp
The file was modifiedllvm/lib/CodeGen/RegAllocPBQP.cpp
The file was modifiedllvm/lib/CodeGen/LiveRangeEdit.cpp
Commit ea058d289cbf54e5b33aac7f7a13d0d58625f1b9 by flo
[VPlan] Use operands for printing of VPWidenMemoryInstructionRecipe.

Now that operands of the recipe are managed through VPUser, we can
simplify the printing by just using the operands.
The file was modifiedllvm/lib/Transforms/Vectorize/VPlan.cpp
The file was modifiedllvm/lib/Transforms/Vectorize/VPlan.h
Commit 43d347995c33a5f48f0b4d9cf3d541a1f6ba66c6 by mtrofin
[NFC][MC] Use MCRegister in LiveRangeMatrix

The change starts from LiveRangeMatrix and also checks the users of the
APIs are typed accordingly.

Differential Revision: https://reviews.llvm.org/D89145
The file was modifiedllvm/lib/CodeGen/LiveRegMatrix.cpp
The file was modifiedllvm/lib/CodeGen/RegAllocBase.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp
The file was modifiedllvm/lib/CodeGen/RegAllocGreedy.cpp
The file was modifiedllvm/lib/Target/AMDGPU/GCNNSAReassign.cpp
The file was modifiedllvm/include/llvm/CodeGen/LiveRegMatrix.h
The file was modifiedllvm/lib/CodeGen/RegAllocBase.h
The file was modifiedllvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp
The file was modifiedllvm/lib/CodeGen/RegAllocBasic.cpp
Commit 2f66bfac280f9ae9299dccc357ae10e8a48525ed by Dávid Bolvanský
[Tests] Regenerate test checks; NFC
The file was modifiedllvm/test/Transforms/InstCombine/cabs-discrete.ll
The file was modifiedllvm/test/Transforms/InstCombine/fabs-libcall.ll
The file was modifiedllvm/test/Transforms/InstCombine/cabs-array.ll
The file was modifiedllvm/test/Transforms/InstCombine/objsize.ll