SuccessChanges

Summary

  1. [DebugInstrRef] Support recording of instruction reference substitutions (details)
  2. Fix unused variable warning when compiling with asserts disabled. (details)
  3. [flang] Fix build with BUILD_SHARED_LIBS=ON and FLANG_BUILD_NEW_DRIVER=ON (details)
  4. [LLD][ELF] Improve ICF for relocations to ineligible sections via "aliases" (details)
  5. [Statepoints] Remove MI limit on number of tied operands. (details)
  6. [SVE]Fix implicit TypeSize casts in EmitCheckValue (details)
  7. [AMDGPU] Minimize number of s_mov generated by copyPhysReg (details)
Commit c521e44defb53d38a46f39e29870c628f25d124a by jeremy.morse
[DebugInstrRef] Support recording of instruction reference substitutions

Add a table recording "substitutions" between pairs of <instruction,
operand> numbers, from old pairs to new pairs. Post-isel optimizations are
able to record the outcome of an optimization in this way. For example, if
there were a divide instruction that generated the quotient and remainder,
and it were replaced by one that only generated the quotient:

  $rax, $rcx = DIV-AND-REMAINDER $rdx, $rsi, debug-instr-num 1
  DBG_INSTR_REF 1, 0
  DBG_INSTR_REF 1, 1

Became:

  $rax = DIV $rdx, $rsi, debug-instr-num 2
  DBG_INSTR_REF 1, 0
  DBG_INSTR_REF 1, 1

We could enter a substitution from <1, 0> to <2, 0>, and no substitution
for <1, 1> as it's no longer generated.

This approach means that if an instruction or value is deleted once we've
left SSA form, all variables that used the value implicitly become
"optimized out", something that isn't true of the current DBG_VALUE
approach.

Differential Revision: https://reviews.llvm.org/D85749
The file was modifiedllvm/include/llvm/CodeGen/MIRYamlMapping.h
The file was modifiedllvm/include/llvm/CodeGen/MachineFunction.h
The file was modifiedllvm/lib/CodeGen/MIRParser/MIRParser.cpp
The file was modifiedllvm/lib/CodeGen/MachineFunction.cpp
The file was addedllvm/test/DebugInfo/MIR/InstrRef/substitusions-roundtrip.mir
The file was modifiedllvm/lib/CodeGen/MIRPrinter.cpp
Commit ead2aa7098cfd693ed1842a88346ba67cfccd7df by akuegel
Fix unused variable warning when compiling with asserts disabled.

Differential Revision: https://reviews.llvm.org/D89454
The file was modifiedllvm/lib/CodeGen/MachineFunction.cpp
Commit 50df5f24dc333e912f6eb8500ef84e648d43af93 by sguelton
[flang] Fix build with BUILD_SHARED_LIBS=ON and FLANG_BUILD_NEW_DRIVER=ON

As usual, it's difficult to handle all different configuration in the first row,
but this one has been extensively tested

Differential Revision: https://reviews.llvm.org/D89452
The file was modifiedflang/unittests/Runtime/CMakeLists.txt
The file was modifiedflang/unittests/Evaluate/CMakeLists.txt
The file was modifiedflang/unittests/Frontend/CMakeLists.txt
The file was modifiedflang/lib/Evaluate/CMakeLists.txt
Commit 88ce27c39c5e42d8a85ac1144d2ae0fae68e8853 by andrew.ng
[LLD][ELF] Improve ICF for relocations to ineligible sections via "aliases"

ICF was not able to merge equivalent sections because of relocations to
sections ineligible for ICF that use alternative symbols, e.g. symbol
aliases or section relative relocations.

Merging in this scenario has been enabled by giving the sections that
are ineligible for ICF a unique ID, i.e. an equivalence class of their
own. This approach also provides another benefit as it improves the
hashing that is used to perform the initial equivalance grouping for
ICF. This is because the ICF ineligible sections can now contribute a
unique value towards the hashes instead of the same value of zero. This
has been seen to reduce link time with ICF by ~68% for objects compiled
with -fprofile-instr-generate.

In order to facilitate this use of a unique ID, the existing
inconsistent approach to the setting of the InputSection eqClass in ICF
has been changed so that there is a clear distinction between the
eqClass values of ICF eligible sections and those of the ineligible
sections that have a unique ID. This inconsistency could have caused
incorrect equivalence class equality in the past, although it appears
that no issues were encountered in actual use.

Differential Revision: https://reviews.llvm.org/D88830
The file was addedlld/test/ELF/icf-ineligible.s
The file was modifiedlld/ELF/ICF.cpp
Commit 8f0ddd4a1a0d2e7b8004d8c3283bddf1a2e27a18 by dantrushin
[Statepoints] Remove MI limit on number of tied operands.

After D87915 statepoint can have more than 15 tied operands.
Remove this restriction from statepoint lowering code.
The file was modifiedllvm/lib/CodeGen/SelectionDAG/StatepointLowering.cpp
The file was addedllvm/test/CodeGen/X86/statepoint-vreg-unlimited-tied-opnds.ll
Commit 145e44bb18853bc9beeac0e64fffd9e6895e71f9 by caroline.concatto
[SVE]Fix implicit TypeSize casts in EmitCheckValue

Using TypeSize::getFixedSize() instead of relying upon the implicit
TypeSize->uint64_cast as the type is always fixed width.

Differential Revision: https://reviews.llvm.org/D89313
The file was modifiedclang/lib/CodeGen/CGExpr.cpp
Commit b70cb5020416413bf5fbfe8111891912153f3034 by carl.ritson
[AMDGPU] Minimize number of s_mov generated by copyPhysReg

Generate the minimal set of s_mov instructions required when
expanding a SGPR copy operation in copyPhysReg.

Reviewed By: foad

Differential Revision: https://reviews.llvm.org/D89187
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/sgpr-phys-copy.mir