SuccessChanges

Summary

  1. [mlir][openacc] Add missing operands for acc.parallel operation (details)
  2. [X86][SSE] Move VZEXT_MOVL(INSERT_SUBVECTOR(UNDEF,X,0)) handling into combineTargetShuffle. (details)
  3. [AMDGPU] Add -show-mc-encoding to setreg tests (details)
  4. [AMDGPU] Enable scheduling around FP MODE-setting instructions (details)
  5. [X86] Assert that we've found a terminator instruction. NFCI. (details)
  6. [AMDGPU] Add v3f16/v3i16 support to SDag (details)
  7. AMDGPU: Improve <2 x i24> arguments and return value handling (details)
  8. [NFC][Regalloc] accessors for 'reg' and 'weight' (details)
  9. [X86] EmitInstrWithCustomInserter - remove redundant getDebugLoc() calls. NFCI. (details)
  10. [ASTMatchers] Add missing definition for decompositionDecl (details)
  11. [AMDGPU] Corrected directive to use for ELF weak refs (details)
  12. [NPM] Translate alias analysis into require<> as well (details)
  13. [llvm][CodeGen] Do not scalarize `llvm.masked.[gather|scatter]` operating on scalable vectors. (details)
  14. [AMDGPU] Remove obsolete comment (details)
  15. [ARM][MVE] Tail-predication: predicate new elementcount checks on force-enabled (details)
  16. [Coro][NewPM] Handle llvm.coro.prepare.retcon in NPM coro-split pass (details)
  17. [libfuzzer] Reduce default verbosity when printing large mutation sequences (details)
  18. Do not apply calling conventions to MSVC entry points (details)
Commit d9953d155493bf11a2276e202800f844a1d02396 by clementval
[mlir][openacc] Add missing operands for acc.parallel operation

Add missing operands to represent copin with readonly modifier, copyout with zero
modifier, create with zero modifier and default clause.

Reviewed By: ftynse

Differential Revision: https://reviews.llvm.org/D87733
The file was modifiedmlir/test/Dialect/OpenACC/ops.mlir
The file was modifiedmlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
The file was modifiedmlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
Commit aa4b0b755a02d69f7f20fddf1d011b0f67a0d207 by llvm-dev
[X86][SSE] Move VZEXT_MOVL(INSERT_SUBVECTOR(UNDEF,X,0)) handling into combineTargetShuffle.

Now that we're getting better at combining shuffles of different vector widths, this can now be performed as part of the standard target shuffle combines and isn't required for cleanup.

Exposed a minor issue in combineX86ShufflesRecursively where we failed to check if a shuffle's src ops were simple types.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit 54bb9e86498010c631a40dbd82617c433beea712 by jay.foad
[AMDGPU] Add -show-mc-encoding to setreg tests

This is a pre-commit for D87446 "[AMDGPU] Enable scheduling around FP MODE-setting instructions"
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.setreg.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.setreg.ll
Commit 90777e2924ec7f99a3f1b718a636f47036012514 by jay.foad
[AMDGPU] Enable scheduling around FP MODE-setting instructions

Pre-gfx10 all MODE-setting instructions were S_SETREG_B32 which is
marked as having unmodeled side effects, which makes the machine
scheduler treat it as a barrier. Now that we have proper implicit $mode
operands we can use a no-side-effects S_SETREG_B32_mode pseudo instead
for setregs that only touch the FP MODE bits, to give the scheduler more
freedom.

Differential Revision: https://reviews.llvm.org/D87446
The file was modifiedllvm/lib/Target/AMDGPU/SIModeRegister.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIFoldOperands.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/frem.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.setreg.ll
The file was modifiedllvm/lib/Target/AMDGPU/SOPInstructions.td
The file was modifiedllvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/fdiv-nofpexcept.ll
Commit cd4615120233c54034b42bafc3d2bcc9f29db63d by llvm-dev
[X86] Assert that we've found a terminator instruction. NFCI.

Fixes clang static analayzer null dereference warning.
The file was modifiedllvm/lib/Target/X86/X86SpeculativeExecutionSideEffectSuppression.cpp
Commit 833b3b0d3a2ff4b8243940eef1a960050ec48682 by sebastian.neubauer
[AMDGPU] Add v3f16/v3i16 support to SDag

Fix lowering and instruction selection for v3x16 types
and enable InstCombine to emit them.

This patch only implements it for the selection dag.
GlobalISel tests in GlobalISel/llvm.amdgcn.image.load.1d.d16.ll and
GlobalISel/llvm.amdgcn.image.store.2d.d16.ll still don't work.

Differential Revision: https://reviews.llvm.org/D84420
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.store.d16.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.load.d16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.d16.dim.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.format.d16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/image-load-d16-tfe.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.format.d16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.store.format.d16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.d16.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.store.format.d16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.format.d16.ll
The file was modifiedllvm/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.td
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
The file was modifiedllvm/lib/Target/AMDGPU/BUFInstructions.td
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.d16.dim.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.load.d16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.load.d16.ll
Commit 71131db6895430d1c027712677a99a573eb7545f by arsenm2
AMDGPU: Improve <2 x i24> arguments and return value handling

This was asserting for GlobalISel. For SelectionDAG, this was
passing this on the stack. Instead, scalarize this as if it were a
32-bit vector.
The file was modifiedllvm/test/CodeGen/AMDGPU/function-args.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/call-return-types.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/fshr.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
Commit 6e85c3d5c786f0d3878d7f79503e8641d1b7030b by mtrofin
[NFC][Regalloc] accessors for 'reg' and 'weight'

Also renamed the fields to follow style guidelines.

Accessors help with readability - weight mutation, in particular,
is easier to follow this way.

Differential Revision: https://reviews.llvm.org/D87725
The file was modifiedllvm/lib/CodeGen/RegAllocPBQP.cpp
The file was modifiedllvm/lib/CodeGen/RegAllocBase.cpp
The file was modifiedllvm/lib/CodeGen/CalcSpillWeights.cpp
The file was modifiedllvm/lib/CodeGen/InlineSpiller.cpp
The file was modifiedllvm/lib/CodeGen/LiveDebugVariables.cpp
The file was modifiedllvm/lib/CodeGen/StackSlotColoring.cpp
The file was modifiedllvm/lib/CodeGen/LiveIntervalUnion.cpp
The file was modifiedllvm/lib/CodeGen/MachineVerifier.cpp
The file was modifiedllvm/lib/CodeGen/LiveIntervals.cpp
The file was modifiedllvm/lib/CodeGen/RenameIndependentSubregs.cpp
The file was modifiedllvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp
The file was modifiedllvm/lib/CodeGen/SplitKit.cpp
The file was modifiedllvm/lib/CodeGen/RegAllocBasic.cpp
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyOptimizeLiveIntervals.cpp
The file was modifiedllvm/include/llvm/CodeGen/LiveRangeEdit.h
The file was modifiedllvm/lib/Target/AMDGPU/GCNNSAReassign.cpp
The file was modifiedllvm/include/llvm/CodeGen/LiveInterval.h
The file was modifiedllvm/lib/CodeGen/LiveIntervalCalc.cpp
The file was modifiedllvm/lib/CodeGen/LiveRegMatrix.cpp
The file was modifiedllvm/lib/CodeGen/LiveRangeEdit.cpp
The file was modifiedllvm/lib/CodeGen/TargetRegisterInfo.cpp
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyRegColoring.cpp
The file was modifiedllvm/lib/CodeGen/RegisterCoalescer.cpp
The file was modifiedllvm/lib/CodeGen/RegAllocGreedy.cpp
The file was modifiedllvm/lib/CodeGen/LiveInterval.cpp
Commit b2c931eff3cd6f88426ef26d233fab1fabaa0b7e by llvm-dev
[X86] EmitInstrWithCustomInserter - remove redundant getDebugLoc() calls. NFCI.

Use the same DebugLoc that is called at the top of the method.

Fixes some Wshadow static analyzer warnings.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit f0546173fa4bdde03ecb21a174fcaa8a6490adbd by benny.kra
[ASTMatchers] Add missing definition for decompositionDecl

Otherwise we'd get a linker error whenever decompositionDecl is ODR
used.
The file was modifiedclang/lib/ASTMatchers/ASTMatchersInternal.cpp
Commit 06d058afecdf54021fbf8fece422dd04766227ea by dmitry.preobrazhensky
[AMDGPU] Corrected directive to use for ELF weak refs

WeakRefDirective should specify a directive to declare "a global as being a weak undefined symbol".
The directive used by AMDGPU was incorrect - ".weakref" was intended for other purposes.
The correct directive is ".weak" and it is already defined as default for ELF.
So the redefinition was removed.

Reviewers: arsenm, rampitec

Differential Revision: https://reviews.llvm.org/D87762
The file was modifiedllvm/test/CodeGen/AMDGPU/hsa-globals.ll
The file was modifiedllvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp
Commit 09c342493d89c2f32602f911e5c919742b837e10 by aeubanks
[NPM] Translate alias analysis into require<> as well

'require<globals-aa>' is needed to make globals-aa work in NPM, since
globals-aa is a module analysis but function passes cannot run module
analyses on demand.
So don't skip translating alias analyses to 'require<>'.

Reviewed By: asbirlea

Differential Revision: https://reviews.llvm.org/D87743
The file was modifiedllvm/lib/Passes/PassBuilder.cpp
The file was modifiedllvm/tools/opt/NewPMDriver.cpp
The file was modifiedllvm/test/Analysis/GlobalsModRef/no-escape.ll
Commit 15e9a6c2118fa3db2c80043e6679da5dcc72b3a7 by francesco.petrogalli
[llvm][CodeGen] Do not scalarize `llvm.masked.[gather|scatter]` operating on scalable vectors.

This patch prevents the `llvm.masked.gather` and `llvm.masked.scatter` intrinsics to be scalarized when invoked on scalable vectors.

The change in `Function.cpp` is needed to prevent the warning that is raised when `getNumElements` is used in place of `getElementCount` on `VectorType` instances. The tests guards for regressions on this change.

The tests makes sure that calls to `llvm.masked.[gather|scatter]` are still scalarized when:

  # the intrinsics are operating on fixed size vectors, and
  # the compiler is not targeting fixed length SVE code generation.

Reviewed By: efriedma, sdesmalen

Differential Revision: https://reviews.llvm.org/D86249
The file was modifiedllvm/lib/IR/Function.cpp
The file was modifiedllvm/lib/CodeGen/ScalarizeMaskedMemIntrin.cpp
The file was addedllvm/test/CodeGen/AArch64/llvm-masked-gather-legal-for-sve.ll
The file was addedllvm/test/CodeGen/AArch64/llvm-masked-scatter-legal-for-sve.ll
Commit cb64455faa36d6ac12759fa4ec4dd05847cb1b90 by jay.foad
[AMDGPU] Remove obsolete comment

Obsoleted by e4464bf3d45848461630e3771d66546d389f1ed5 "AMDGPU/GlobalISel: Select scalar v2s16 G_BUILD_VECTOR"
The file was modifiedllvm/lib/Target/AMDGPU/SIInstructions.td
Commit b5c3efeb7bc9861dc04a1b00a4c0183bdfa9b582 by sjoerd.meijer
[ARM][MVE] Tail-predication: predicate new elementcount checks on force-enabled

Additional sanity checks were added to get.active.lane.mask's second argument,
the loop tripcount/elementcount, in rG635b87511ec3. Like the other (overflow)
checks, skip this if tail-predication is forced.

Differential Revision: https://reviews.llvm.org/D87769
The file was modifiedllvm/lib/Target/ARM/MVETailPredication.cpp
Commit c27b64bbe1bf96642b5b1e0babde7886bb30c84f by aeubanks
[Coro][NewPM] Handle llvm.coro.prepare.retcon in NPM coro-split pass

Reviewed By: rjmccall

Differential Revision: https://reviews.llvm.org/D87731
The file was modifiedllvm/lib/Transforms/Coroutines/CoroSplit.cpp
The file was modifiedllvm/test/Transforms/Coroutines/coro-retcon-frame.ll
Commit 66df98945e08906ce4a057245fda81f631cfd3ae by mascasa
[libfuzzer] Reduce default verbosity when printing large mutation sequences

When using a custom mutator (e.g. thrift mutator, similar to LPM)
that calls back into libfuzzer's mutations via `LLVMFuzzerMutate`, the mutation
sequences needed to achieve new coverage can get prohibitively large.

Printing these large sequences has two downsides:

1) It makes the logs hard to understand for a human.
2) The performance cost slows down fuzzing.

In this patch I change the `PrintMutationSequence` function to take a max
number of entries, to achieve this goal. I also update `PrintStatusForNewUnit`
to default to printing only 10 entries, in the default verbosity level (1),
requiring the user to set verbosity to 2 if they want the full mutation
sequence.

For our use case, turning off verbosity is not an option, as that would also
disable `PrintStats()` which is very useful for infrastructure that analyzes
the logs in realtime. I imagine most users of libfuzzer always want those logs
in the default.

I built a fuzzer locally with this patch applied to libfuzzer.

When running with the default verbosity, I see logs like this:

    #65 NEW    cov: 4799 ft: 10443 corp: 41/1447Kb lim: 64000 exec/s: 1 rss: 575Mb L: 28658/62542 MS: 196 Custom-CrossOver-ChangeBit-EraseBytes-ChangeBit-ChangeBit-ChangeBit-CrossOver-ChangeBit-CrossOver- DE: "\xff\xff\xff\x0e"-"\xfe\xff\xff\x7f"-"\xfe\xff\xff\x7f"-"\x17\x00\x00\x00\x00\x00\x00\x00"-"\x00\x00\x00\xf9"-"\xff\xff\xff\xff"-"\xfa\xff\xff\xff"-"\xf7\xff\xff\xff"-"@\xff\xff\xff\xff\xff\xff\xff"-"E\x00"-
    #67 NEW    cov: 4810 ft: 10462 corp: 42/1486Kb lim: 64000 exec/s: 1 rss: 577Mb L: 39823/62542 MS: 135 Custom-CopyPart-ShuffleBytes-ShuffleBytes-ChangeBit-ChangeBinInt-EraseBytes-ChangeBit-ChangeBinInt-ChangeBit- DE: "\x01\x00\x00\x00\x00\x00\x01\xf1"-"\x00\x00\x00\x07"-"\x00\x0d"-"\xfd\xff\xff\xff"-"\xfe\xff\xff\xf4"-"\xe3\xff\xff\xff"-"\xff\xff\xff\xf1"-"\xea\xff\xff\xff"-"\x00\x00\x00\xfd"-"\x01\x00\x00\x05"-

Staring hard at the logs it's clear that the cap of 10 is applied.

When running with verbosity level 2, the logs look like the below:

    #66    NEW    cov: 4700 ft: 10188 corp: 37/1186Kb lim: 64000 exec/s: 2 rss: 509Mb L: 47616/61231 MS: 520 Custom-CopyPart-ChangeBinInt-ChangeBit-ChangeByte-EraseBytes-PersAutoDict-CopyPart-ShuffleBytes-ChangeBit-ShuffleBytes-CopyPart-EraseBytes-CopyPart-ChangeBinInt-CopyPart-ChangeByte-ShuffleBytes-ChangeBinInt-ShuffleBytes-ChangeBit-CMP-ShuffleBytes-ChangeBit-CrossOver-ChangeBinInt-ChangeByte-ShuffleBytes-CrossOver-EraseBytes-ChangeBinInt-InsertRepeatedBytes-PersAutoDict-InsertRepeatedBytes-InsertRepeatedBytes-CrossOver-ChangeByte-ShuffleBytes-CopyPart-ShuffleBytes-CopyPart-CrossOver-ChangeBit-ShuffleBytes-CrossOver-PersAutoDict-ChangeByte-ChangeBit-ShuffleBytes-CrossOver-ChangeByte-EraseBytes-CopyPart-ChangeBinInt-PersAutoDict-CrossOver-ShuffleBytes-CrossOver-CrossOver-EraseBytes-CrossOver-EraseBytes-CrossOver-ChangeBit-ChangeBinInt-ChangeByte-EraseBytes-ShuffleBytes-ShuffleBytes-ChangeBit-EraseBytes-ChangeBinInt-ChangeBit-ChangeBinInt-CopyPart-EraseBytes-PersAutoDict-EraseBytes-CopyPart-ChangeBinInt-ChangeByte-CrossOver-ChangeBinInt-ShuffleBytes-PersAutoDict-PersAutoDict-ChangeBinInt-CopyPart-ChangeBinInt-CrossOver-ChangeBit-ChangeBinInt-CopyPart-ChangeByte-ChangeBit-CopyPart-CrossOver-ChangeByte-ChangeBit-ChangeByte-ShuffleBytes-CMP-ChangeBit-CopyPart-ChangeBit-ChangeByte-ChangeBinInt-PersAutoDict-ChangeBinInt-CrossOver-ChangeBinInt-ChangeBit-ChangeBinInt-ChangeBinInt-PersAutoDict-ChangeBinInt-ChangeBinInt-ChangeByte-CopyPart-ShuffleBytes-ChangeByte-ChangeBit-ChangeByte-ChangeByte-EraseBytes-CrossOver-ChangeByte-ChangeByte-EraseBytes-EraseBytes-InsertRepeatedBytes-ShuffleBytes-CopyPart-CopyPart-ChangeBit-ShuffleBytes-PersAutoDict-ShuffleBytes-ChangeBit-ChangeByte-ChangeBit-ShuffleBytes-ChangeByte-ChangeBinInt-CrossOver-ChangeBinInt-ChangeBit-EraseBytes-CopyPart-ChangeByte-CrossOver-EraseBytes-CrossOver-ChangeByte-ShuffleBytes-ChangeByte-ChangeBinInt-CrossOver-ChangeByte-InsertRepeatedBytes-InsertByte-ShuffleBytes-PersAutoDict-ChangeBit-ChangeByte-ChangeBit-ShuffleBytes-ShuffleBytes-CopyPart-ShuffleBytes-EraseBytes-ShuffleBytes-ShuffleBytes-CrossOver-ChangeBinInt-CopyPart-CopyPart-CopyPart-EraseBytes-EraseBytes-ChangeByte-ChangeBinInt-ShuffleBytes-CMP-InsertByte-EraseBytes-ShuffleBytes-CopyPart-ChangeBit-CrossOver-CopyPart-CopyPart-ShuffleBytes-ChangeByte-ChangeByte-ChangeBinInt-EraseBytes-ChangeByte-ChangeBinInt-ChangeBit-ChangeBit-ChangeByte-ShuffleBytes-PersAutoDict-PersAutoDict-CMP-ChangeBit-ShuffleBytes-PersAutoDict-ChangeBinInt-EraseBytes-EraseBytes-ShuffleBytes-ChangeByte-ShuffleBytes-ChangeBit-EraseBytes-CMP-ShuffleBytes-ChangeByte-ChangeBinInt-EraseBytes-ChangeBinInt-ChangeByte-EraseBytes-ChangeByte-CrossOver-ShuffleBytes-EraseBytes-EraseBytes-ShuffleBytes-ChangeBit-EraseBytes-CopyPart-ShuffleBytes-ShuffleBytes-CrossOver-CopyPart-ChangeBinInt-ShuffleBytes-CrossOver-InsertByte-InsertByte-ChangeBinInt-ChangeBinInt-CopyPart-EraseBytes-ShuffleBytes-ChangeBit-ChangeBit-EraseBytes-ChangeByte-ChangeByte-ChangeBinInt-CrossOver-ChangeBinInt-ChangeBinInt-ShuffleBytes-ShuffleBytes-ChangeByte-ChangeByte-ChangeBinInt-ShuffleBytes-CrossOver-EraseBytes-CopyPart-CopyPart-CopyPart-ChangeBit-ShuffleBytes-ChangeByte-EraseBytes-ChangeByte-InsertRepeatedBytes-InsertByte-InsertRepeatedBytes-PersAutoDict-EraseBytes-ShuffleBytes-ChangeByte-ShuffleBytes-ChangeBinInt-ShuffleBytes-ChangeBinInt-ChangeBit-CrossOver-CrossOver-ShuffleBytes-CrossOver-CopyPart-CrossOver-CrossOver-CopyPart-ChangeByte-ChangeByte-CrossOver-ChangeBit-ChangeBinInt-EraseBytes-ShuffleBytes-EraseBytes-CMP-PersAutoDict-PersAutoDict-InsertByte-ChangeBit-ChangeByte-CopyPart-CrossOver-ChangeByte-ChangeBit-ChangeByte-CopyPart-ChangeBinInt-EraseBytes-CrossOver-ChangeBit-CrossOver-PersAutoDict-CrossOver-ChangeByte-CrossOver-ChangeByte-ChangeByte-CrossOver-ShuffleBytes-CopyPart-CopyPart-ShuffleBytes-ChangeByte-ChangeByte-ChangeBinInt-ChangeBinInt-ChangeBinInt-ChangeBinInt-ShuffleBytes-CrossOver-ChangeBinInt-ShuffleBytes-ChangeBit-PersAutoDict-ChangeBinInt-ShuffleBytes-ChangeBinInt-ChangeByte-CrossOver-ChangeBit-CopyPart-ChangeBit-ChangeBit-CopyPart-ChangeByte-PersAutoDict-ChangeBit-ShuffleBytes-ChangeByte-ChangeBit-CrossOver-ChangeByte-CrossOver-ChangeByte-CrossOver-ChangeBit-ChangeByte-ChangeBinInt-PersAutoDict-CopyPart-ChangeBinInt-ChangeBit-CrossOver-ChangeBit-PersAutoDict-ShuffleBytes-EraseBytes-CrossOver-ChangeByte-ChangeBinInt-ShuffleBytes-ChangeBinInt-InsertRepeatedBytes-PersAutoDict-CrossOver-ChangeByte-Custom-PersAutoDict-CopyPart-CopyPart-ChangeBinInt-ShuffleBytes-ChangeBinInt-ChangeBit-ShuffleBytes-CrossOver-CMP-ChangeByte-CopyPart-ShuffleBytes-CopyPart-CopyPart-CrossOver-CrossOver-CrossOver-ShuffleBytes-ChangeByte-ChangeBinInt-ChangeBit-ChangeBit-ChangeBit-ChangeByte-EraseBytes-ChangeByte-ChangeBit-ChangeByte-ChangeByte-CopyPart-PersAutoDict-ChangeBinInt-PersAutoDict-PersAutoDict-PersAutoDict-CopyPart-CopyPart-CrossOver-ChangeByte-ChangeBinInt-ShuffleBytes-ChangeBit-CopyPart-EraseBytes-CopyPart-CopyPart-CrossOver-ChangeByte-EraseBytes-ShuffleBytes-ChangeByte-CopyPart-EraseBytes-CopyPart-CrossOver-ChangeBinInt-ChangeBinInt-InsertByte-ChangeBinInt-ChangeBit-ChangeByte-CopyPart-ChangeByte-EraseBytes-ChangeByte-ChangeBit-ChangeByte-ShuffleBytes-CopyPart-ChangeBinInt-EraseBytes-CrossOver-ChangeBit-ChangeBit-CrossOver-EraseBytes-ChangeBinInt-CopyPart-CopyPart-ChangeBinInt-ChangeBit-EraseBytes-InsertRepeatedBytes-EraseBytes-ChangeBit-CrossOver-CrossOver-EraseBytes-EraseBytes-ChangeByte-CopyPart-CopyPart-ShuffleBytes-ChangeByte-ChangeBit-ChangeByte-EraseBytes-ChangeBit-ChangeByte-ChangeByte-CrossOver-CopyPart-EraseBytes-ChangeByte-EraseBytes-ChangeByte-ShuffleBytes-ShuffleBytes-ChangeByte-CopyPart-ChangeByte-ChangeByte-ChangeBit-CopyPart-ChangeBit-ChangeBinInt-CopyPart-ShuffleBytes-ChangeBit-ChangeBinInt-ChangeBit-EraseBytes-CMP-CrossOver-CopyPart-ChangeBinInt-CrossOver-CrossOver-CopyPart-CrossOver-CrossOver-InsertByte-InsertByte-CopyPart-Custom- DE: "warn"-"\x00\x00\x00\x80"-"\xfe\xff\xff\xfb"-"\xff\xff"-"\x10\x00\x00\x00"-"\xfe\xff\xff\xff"-"\xff\xff\xff\xf6"-"U\x01\x00\x00\x00\x00\x00\x00"-"\xd9\xff\xff\xff"-"\xfe\xff\xff\xea"-"\xf0\xff\xff\xff"-"\xfc\xff\xff\xff"-"warn"-"\xff\xff\xff\xff"-"\xfe\xff\xff\xfb"-"\x00\x00\x00\x80"-"\xfe\xff\xff\xf1"-"\xfe\xff\xff\xea"-"\x00\x00\x00\x00\x00\x00\x012"-"\xe2\x00"-"\xfb\xff\xff\xff"-"\x00\x00\x00\x00"-"\xe9\xff\xff\xff"-"\xff\xff"-"\x00\x00\x00\x80"-"\x01\x00\x04\xc9"-"\xf0\xff\xff\xff"-"\xf9\xff\xff\xff"-"\xff\xff\xff\xff\xff\xff\xff\x12"-"\xe2\x00"-"\xfe\xff\xff\xff"-"\xfe\xff\xff\xea"-"\xff\xff\xff\xff"-"\xf4\xff\xff\xff"-"\xe9\xff\xff\xff"-"\xf1\xff\xff\xff"-
    #48    NEW    cov: 4502 ft: 9151 corp: 27/750Kb lim: 64000 exec/s: 2 rss: 458Mb L: 50772/50772 MS: 259 ChangeByte-ShuffleBytes-ChangeBinInt-ChangeByte-ChangeByte-ChangeByte-ChangeByte-ChangeBit-CopyPart-CrossOver-CopyPart-ChangeByte-CrossOver-CopyPart-ChangeBit-ChangeByte-EraseBytes-ChangeByte-CopyPart-CopyPart-CopyPart-ChangeBit-EraseBytes-ChangeBinInt-CrossOver-CopyPart-CrossOver-CopyPart-ChangeBit-ChangeByte-ChangeBit-InsertByte-CrossOver-InsertRepeatedBytes-InsertRepeatedBytes-InsertRepeatedBytes-ChangeBinInt-EraseBytes-InsertRepeatedBytes-InsertByte-ChangeBit-ShuffleBytes-ChangeBit-ChangeBit-CopyPart-ChangeBit-ChangeByte-CrossOver-ChangeBinInt-ChangeByte-CrossOver-CMP-ChangeByte-CrossOver-ChangeByte-ShuffleBytes-ShuffleBytes-ChangeByte-ChangeBinInt-CopyPart-EraseBytes-CrossOver-ChangeBit-ChangeBinInt-InsertByte-ChangeBit-CopyPart-ChangeBinInt-ChangeByte-CrossOver-ChangeBit-EraseBytes-CopyPart-ChangeBinInt-ChangeBit-ChangeBit-ChangeByte-CopyPart-ChangeBinInt-CrossOver-PersAutoDict-ChangeByte-ChangeBit-ChangeByte-ChangeBinInt-ChangeBinInt-EraseBytes-CopyPart-CopyPart-ChangeByte-ChangeByte-EraseBytes-PersAutoDict-CopyPart-ChangeByte-ChangeByte-EraseBytes-CrossOver-CopyPart-CopyPart-CopyPart-ChangeByte-ChangeBit-CMP-CopyPart-ChangeBinInt-ChangeBinInt-CrossOver-ChangeBit-ChangeBit-EraseBytes-ChangeByte-ShuffleBytes-ChangeBit-ChangeBinInt-CMP-InsertRepeatedBytes-CopyPart-Custom-ChangeByte-CrossOver-EraseBytes-ChangeBit-CopyPart-CrossOver-CMP-ShuffleBytes-EraseBytes-CrossOver-PersAutoDict-ChangeByte-CrossOver-CopyPart-CrossOver-CrossOver-ShuffleBytes-ChangeBinInt-CrossOver-ChangeBinInt-ShuffleBytes-PersAutoDict-ChangeByte-EraseBytes-ChangeBit-CrossOver-EraseBytes-CrossOver-ChangeBit-ChangeBinInt-EraseBytes-InsertByte-InsertRepeatedBytes-InsertByte-InsertByte-ChangeByte-ChangeBinInt-ChangeBit-CrossOver-ChangeByte-CrossOver-EraseBytes-ChangeByte-ShuffleBytes-ChangeBit-ChangeBit-ShuffleBytes-CopyPart-ChangeByte-PersAutoDict-ChangeBit-ChangeByte-InsertRepeatedBytes-CMP-CrossOver-ChangeByte-EraseBytes-ShuffleBytes-CrossOver-ShuffleBytes-ChangeBinInt-ChangeBinInt-CopyPart-PersAutoDict-ShuffleBytes-ChangeBit-CopyPart-ShuffleBytes-CopyPart-EraseBytes-ChangeByte-ChangeBit-ChangeBit-ChangeBinInt-ChangeByte-CopyPart-EraseBytes-ChangeBinInt-EraseBytes-EraseBytes-PersAutoDict-CMP-PersAutoDict-CrossOver-CrossOver-ChangeBit-CrossOver-PersAutoDict-CrossOver-CopyPart-ChangeByte-EraseBytes-ChangeByte-ShuffleBytes-ChangeByte-ChangeByte-CrossOver-ChangeBit-EraseBytes-ChangeByte-EraseBytes-ChangeBinInt-CrossOver-CrossOver-EraseBytes-ChangeBinInt-CrossOver-ChangeBit-ShuffleBytes-ChangeBit-ChangeByte-EraseBytes-ChangeBit-CrossOver-CrossOver-CrossOver-ChangeByte-ChangeBit-ShuffleBytes-ChangeBit-ChangeBit-EraseBytes-CrossOver-CrossOver-CopyPart-ShuffleBytes-ChangeByte-ChangeByte-CopyPart-CrossOver-CopyPart-CrossOver-CrossOver-EraseBytes-EraseBytes-ShuffleBytes-InsertRepeatedBytes-ChangeBit-CopyPart-Custom- DE: "\xfe\xff\xff\xfc"-"\x00\x00\x00\x00"-"F\x00"-"\xf3\xff\xff\xff"-"St9exception"-"_\x00\x00\x00"-"\xf6\xff\xff\xff"-"\xfe\xff\xff\xff"-"\x00\x00\x00\x00"-"p\x02\x00\x00\x00\x00\x00\x00"-"\xfe\xff\xff\xfb"-"\xff\xff"-"\xff\xff\xff\xff"-"\x01\x00\x00\x07"-"\xfe\xff\xff\xfe"-

These are prohibitively large and of limited value in the default case (when
someone is running the fuzzer, not debugging it), in my opinion.

Reviewed By: morehouse

Differential Revision: https://reviews.llvm.org/D86658
The file was addedcompiler-rt/test/fuzzer/CustomMutatorWithLongSequencesTest.cpp
The file was modifiedcompiler-rt/test/fuzzer/fuzzer-custommutator.test
The file was modifiedcompiler-rt/lib/fuzzer/FuzzerLoop.cpp
The file was modifiedcompiler-rt/lib/fuzzer/FuzzerMutate.h
The file was modifiedcompiler-rt/lib/fuzzer/FuzzerMutate.cpp
Commit 4cff1b40dacf6a5489b09657d94ea4757b8cd3b0 by elizabeth.andrews
Do not apply calling conventions to MSVC entry points

Fix link error for MSVC entry points when calling conventions
are specified. MSVC entry points should have default calling
convention.

Differential Revision: https://reviews.llvm.org/D87701
The file was modifiedclang/test/CodeGenCXX/default_calling_conv.cpp
The file was modifiedclang/lib/Sema/SemaDecl.cpp