AbortedChanges

Summary

  1. Merging r313392: ------------------------------------------------------------------------ r313392 | ctopper | 2017-09-15 13:27:59 -0700 (Fri, 15 Sep 2017) | 7 lines [X86] Disable _mm512_maskz_set1_epi64 intrinsic on 32-bit targets to prevent a backend isel failure. The __builtin_ia32_pbroadcastq512_mem_mask we were previously trying to use in 32-bit mode is not implemented in the x86 backend and causes isel to fail in release builds. In debug builds it fails even earlier during legalization with an llvm_unreachable. While there add the missing test case for this intrinsic for this for 64-bit mode. This fixes PR34631. D37668 should be able to recover this for 32-bit mode soon. But I wanted to fix the crash ahead of that. ------------------------------------------------------------------------
  2. Merging r314252: ------------------------------------------------------------------------ r314252 | gberry | 2017-09-26 14:40:46 -0700 (Tue, 26 Sep 2017) | 12 lines [AArch64][Falkor] Fix bug in falkor prefetcher fix pass. Summary: In rare cases, loads that don't get prefetched that were marked as strided loads could cause a crash if they occurred in a loop with other colliding loads. Reviewers: mcrosier Subscribers: aemerson, rengolin, javed.absar, kristof.beyls Differential Revision: https://reviews.llvm.org/D38261 ------------------------------------------------------------------------
  3. Merging r314251: ------------------------------------------------------------------------ r314251 | gberry | 2017-09-26 14:40:41 -0700 (Tue, 26 Sep 2017) | 16 lines [AArch64][Falkor] Fix correctness bug in falkor prefetcher fix pass and correct some opcode tag computations. Summary: This addresses a correctness bug for LD[1234]*_POST opcodes that have the prefetcher fix applied to them: the base register was not being written back from the temp after being incremented, so it would appear to never be incremented. Also, fix some opcode tag computations based on some updated HW details to get better tag avoidance and thus better prefetcher performance. Reviewers: mcrosier Subscribers: aemerson, rengolin, javed.absar, kristof.beyls Differential Revision: https://reviews.llvm.org/D38256 ------------------------------------------------------------------------
  4. Merging r311599: ------------------------------------------------------------------------ r311599 | gberry | 2017-08-23 14:11:28 -0700 (Wed, 23 Aug 2017) | 4 lines [AArch64][Falkor] Fix bug in Falkor HWPF tag collision avoidance LDPDi was incorrectly marked as ignoring the destination register in the prefetcher tag. ------------------------------------------------------------------------
  5. [llvmlab] Add timeout and retries for fetching builds. In case of network problems, time out after 5 seconds instead of relying on OS to close the connection which can take more than 20 minutes. Timeout value is measured between successfully transmitted packets, not for entire transaction. So we don't require big files to be downloaded in 5 seconds but we require not to get stuck for more than 5 seconds. Reviewers: cmatthews, JDevlieghere Reviewed By: cmatthews Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38281
Revision 314569 by tstellar:
Merging r313392:

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r313392 | ctopper | 2017-09-15 13:27:59 -0700 (Fri, 15 Sep 2017) | 7 lines

[X86] Disable _mm512_maskz_set1_epi64 intrinsic on 32-bit targets to prevent a backend isel failure.

The __builtin_ia32_pbroadcastq512_mem_mask we were previously trying to use in 32-bit mode is not implemented in the x86 backend and causes isel to fail in release builds. In debug builds it fails even earlier during legalization with an llvm_unreachable.

While there add the missing test case for this intrinsic for this for 64-bit mode.

This fixes PR34631. D37668 should be able to recover this for 32-bit mode soon. But I wanted to fix the crash ahead of that.
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Change TypePath in RepositoryPath in Workspace
The file was modified/cfe/branches/release_50/include/clang/Basic/BuiltinsX86.defclang.src/include/clang/Basic/BuiltinsX86.def
The file was modified/cfe/branches/release_50/lib/Headers/avx512fintrin.hclang.src/lib/Headers/avx512fintrin.h
The file was modified/cfe/branches/release_50/test/CodeGen/avx512f-builtins.cclang.src/test/CodeGen/avx512f-builtins.c
Revision 314555 by tstellar:
Merging r314252:

------------------------------------------------------------------------
r314252 | gberry | 2017-09-26 14:40:46 -0700 (Tue, 26 Sep 2017) | 12 lines

[AArch64][Falkor] Fix bug in falkor prefetcher fix pass.

Summary:
In rare cases, loads that don't get prefetched that were marked as
strided loads could cause a crash if they occurred in a loop with other
colliding loads.

Reviewers: mcrosier

Subscribers: aemerson, rengolin, javed.absar, kristof.beyls

Differential Revision: https://reviews.llvm.org/D38261
------------------------------------------------------------------------
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/branches/release_50/lib/Target/AArch64/AArch64FalkorHWPFFix.cppllvm.src/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp
The file was modified/llvm/branches/release_50/test/CodeGen/AArch64/falkor-hwpf-fix.mirllvm.src/test/CodeGen/AArch64/falkor-hwpf-fix.mir
Revision 314554 by tstellar:
Merging r314251:

------------------------------------------------------------------------
r314251 | gberry | 2017-09-26 14:40:41 -0700 (Tue, 26 Sep 2017) | 16 lines

[AArch64][Falkor] Fix correctness bug in falkor prefetcher fix pass and correct some opcode tag computations.

Summary:
This addresses a correctness bug for LD[1234]*_POST opcodes that have
the prefetcher fix applied to them: the base register was not being
written back from the temp after being incremented, so it would appear
to never be incremented.

Also, fix some opcode tag computations based on some updated HW details
to get better tag avoidance and thus better prefetcher performance.

Reviewers: mcrosier

Subscribers: aemerson, rengolin, javed.absar, kristof.beyls

Differential Revision: https://reviews.llvm.org/D38256
------------------------------------------------------------------------
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/branches/release_50/lib/Target/AArch64/AArch64FalkorHWPFFix.cppllvm.src/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp
The file was modified/llvm/branches/release_50/test/CodeGen/AArch64/falkor-hwpf-fix.mirllvm.src/test/CodeGen/AArch64/falkor-hwpf-fix.mir
Revision 314553 by tstellar:
Merging r311599:

------------------------------------------------------------------------
r311599 | gberry | 2017-08-23 14:11:28 -0700 (Wed, 23 Aug 2017) | 4 lines

[AArch64][Falkor] Fix bug in Falkor HWPF tag collision avoidance

LDPDi was incorrectly marked as ignoring the destination register in the
prefetcher tag.
------------------------------------------------------------------------
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/branches/release_50/lib/Target/AArch64/AArch64FalkorHWPFFix.cppllvm.src/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp
Revision 314540 by vsapsai:
[llvmlab] Add timeout and retries for fetching builds.

In case of network problems, time out after 5 seconds instead of relying on OS
to close the connection which can take more than 20 minutes. Timeout value is
measured between successfully transmitted packets, not for entire transaction.
So we don't require big files to be downloaded in 5 seconds but we require not
to get stuck for more than 5 seconds.

Reviewers: cmatthews, JDevlieghere

Reviewed By: cmatthews

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D38281
Change TypePath in RepositoryPath in Workspace
The file was modified/zorg/trunk/llvmbisect/llvmlab/gcs.pyzorg/llvmbisect/llvmlab/gcs.py