AbortedChanges

Summary

  1. Merging r310552: ------------------------------------------------------------------------ r310552 | eladcohen | 2017-08-10 00:44:23 -0700 (Thu, 10 Aug 2017) | 19 lines [SelectionDAG] When scalarizing vselect, don't assert on a legal cond operand. When scalarizing the result of a vselect, the legalizer currently expects to already have scalarized the operands. While this is true for the true/false operands (which have the same type as the result), it is not case for the condition operand. On X86 AVX512, v1i1 is legal - this leads to operations such as '< N x type> vselect < N x i1> < N x type> < N x type>' where < N x type > is illegal to hit an assertion during the scalarization. The handling is similar to r205625. This also exposes the fact that (v1i1 extract_subvector) should be legal and selectable on AVX512 - We do this by custom lowering to vector_extract_elt. This still leaves us in some cases with redundant dag nodes which will be combined in a separate soon to come patch. This fixes pr33349. Differential revision: https://reviews.llvm.org/D36511 ------------------------------------------------------------------------
  2. Merging r310481, r310492 and r310510: ------------------------------------------------------------------------ r310481 | davide | 2017-08-09 08:13:50 -0700 (Wed, 09 Aug 2017) | 8 lines [ValueTracking] Honour recursion limit. The recently improved support for `icmp` in ValueTracking (r307304) exposes the fact that `isImplied` condition doesn't really bail out if we hit the recursion limit (and calls `computeKnownBits` which increases the depth and asserts). Differential Revision: https://reviews.llvm.org/D36512 ------------------------------------------------------------------------ ------------------------------------------------------------------------ r310492 | davide | 2017-08-09 09:06:04 -0700 (Wed, 09 Aug 2017) | 1 line [ValueTracking] Update tests to unbreak the bots. ------------------------------------------------------------------------ ------------------------------------------------------------------------ r310510 | spatel | 2017-08-09 11:56:26 -0700 (Wed, 09 Aug 2017) | 6 lines [SimplifyCFG] remove checks for crasher test from r310481 Not sure why the earlier version would fail, but trying to get the bots (and my local machine) to pass again. ------------------------------------------------------------------------
  3. Merging r308847: ------------------------------------------------------------------------ r308847 | mkazantsev | 2017-07-23 08:40:19 -0700 (Sun, 23 Jul 2017) | 24 lines [SCEV] Limit max size of AddRecExpr during evolving When SCEV calculates product of two SCEVAddRecs from the same loop, it tries to combine them into one big AddRecExpr. If the sizes of the initial SCEVs were `S1` and `S2`, the size of their product is `S1 + S2 - 1`, and every operand of the resulting SCEV is combined from operands of initial SCEV and has much higher complexity than they have. As result, if we try to calculate something like: %x1 = {a,+,b} %x2 = mul i32 %x1, %x1 %x3 = mul i32 %x2, %x1 %x4 = mul i32 %x3, %x2 ... The size of such SCEVs grows as `2^N`, and the arguments become more and more complex as we go forth. This leads to long compilation and huge memory consumption. This patch sets a limit after which we don't try to combine two `SCEVAddRecExpr`s into one. By default, max allowed size of the resulting AddRecExpr is set to 16. Differential Revision: https://reviews.llvm.org/D35664 ------------------------------------------------------------------------
  4. Merging r310534: ------------------------------------------------------------------------ r310534 | matze | 2017-08-09 15:22:05 -0700 (Wed, 09 Aug 2017) | 20 lines ARM: Fix CMP_SWAP expansion Clean up after my misguided attempt in r304267 to "fix" CMP_SWAP returning an uninitialized status value. - I was always using tMOVi8 to zero the status register which cannot encode higher register numbers and llvm would silently miscompile) - Nobody was ever looking at that status value outside the expansion. ARMDAGToDAGISel::SelectCMP_SWAP() the only place creating CMP_SWAP instructions was not mapping anything to it. (The cmpxchg status value from llvm IR is lowered to a manual comparison after the CMP_SWAP) So this: - Renames the register from "status" to "temp" it make it obvious that it isn't used outside the expansion. - Remove the zeroing status/temp register. - Keep the live-in list improvements from r304267 Fixes http://llvm.org/PR34056 ------------------------------------------------------------------------
Revision 310635 by hans:
Merging r310552:
------------------------------------------------------------------------
r310552 | eladcohen | 2017-08-10 00:44:23 -0700 (Thu, 10 Aug 2017) | 19 lines

[SelectionDAG] When scalarizing vselect, don't assert on
a legal cond operand.

When scalarizing the result of a vselect, the legalizer currently expects
to already have scalarized the operands. While this is true for the true/false
operands (which have the same type as the result), it is not case for the
condition operand. On X86 AVX512, v1i1 is legal - this leads to operations such
as '< N x type> vselect < N x i1> < N x type> < N x type>' where < N x type > is
illegal to hit an assertion during the scalarization.

The handling is similar to r205625.
This also exposes the fact that (v1i1 extract_subvector) should be legal
and selectable on AVX512 - We do this by custom lowering to vector_extract_elt.
This still leaves us in some cases with redundant dag nodes which will be
combined in a separate soon to come patch.

This fixes pr33349.

Differential revision: https://reviews.llvm.org/D36511
------------------------------------------------------------------------
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/branches/release_50llvm.src
The file was modified/llvm/branches/release_50/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cppllvm.src/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
The file was modified/llvm/branches/release_50/lib/Target/X86/X86ISelLowering.cppllvm.src/lib/Target/X86/X86ISelLowering.cpp
The file was added/llvm/branches/release_50/test/CodeGen/X86/pr33349.llllvm.src/test/CodeGen/X86/pr33349.ll
Revision 310634 by hans:
Merging r310481, r310492 and r310510:
------------------------------------------------------------------------
r310481 | davide | 2017-08-09 08:13:50 -0700 (Wed, 09 Aug 2017) | 8 lines

[ValueTracking] Honour recursion limit.

The recently improved support for `icmp` in ValueTracking
(r307304) exposes the fact that `isImplied` condition doesn't
really bail out if we hit the recursion limit (and calls
`computeKnownBits` which increases the depth and asserts).

Differential Revision:  https://reviews.llvm.org/D36512
------------------------------------------------------------------------

------------------------------------------------------------------------
r310492 | davide | 2017-08-09 09:06:04 -0700 (Wed, 09 Aug 2017) | 1 line

[ValueTracking] Update tests to unbreak the bots.
------------------------------------------------------------------------

------------------------------------------------------------------------
r310510 | spatel | 2017-08-09 11:56:26 -0700 (Wed, 09 Aug 2017) | 6 lines

[SimplifyCFG] remove checks for crasher test from r310481

Not sure why the earlier version would fail, but trying to get the bots
(and my local machine) to pass again.


------------------------------------------------------------------------
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/branches/release_50llvm.src
The file was modified/llvm/branches/release_50/lib/Analysis/ValueTracking.cppllvm.src/lib/Analysis/ValueTracking.cpp
The file was added/llvm/branches/release_50/test/Transforms/SimplifyCFG/pr34131.llllvm.src/test/Transforms/SimplifyCFG/pr34131.ll
Revision 310629 by hans:
Merging r308847:
------------------------------------------------------------------------
r308847 | mkazantsev | 2017-07-23 08:40:19 -0700 (Sun, 23 Jul 2017) | 24 lines

[SCEV] Limit max size of AddRecExpr during evolving

When SCEV calculates product of two SCEVAddRecs from the same loop, it
tries to combine them into one big AddRecExpr. If the sizes of the initial
SCEVs were `S1` and `S2`, the size of their product is `S1 + S2 - 1`, and every
operand of the resulting SCEV is combined from operands of initial SCEV and
has much higher complexity than they have.

As result, if we try to calculate something like:
  %x1 = {a,+,b}
  %x2 = mul i32 %x1, %x1
  %x3 = mul i32 %x2, %x1
  %x4 = mul i32 %x3, %x2
  ...
The size of such SCEVs grows as `2^N`, and the arguments
become more and more complex as we go forth. This leads
to long compilation and huge memory consumption.

This patch sets a limit after which we don't try to combine two
`SCEVAddRecExpr`s into one. By default, max allowed size of the
resulting AddRecExpr is set to 16.

Differential Revision: https://reviews.llvm.org/D35664

------------------------------------------------------------------------
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/branches/release_50llvm.src
The file was modified/llvm/branches/release_50/lib/Analysis/ScalarEvolution.cppllvm.src/lib/Analysis/ScalarEvolution.cpp
The file was added/llvm/branches/release_50/test/Analysis/ScalarEvolution/max-addrec-size.llllvm.src/test/Analysis/ScalarEvolution/max-addrec-size.ll
Revision 310628 by hans:
Merging r310534:
------------------------------------------------------------------------
r310534 | matze | 2017-08-09 15:22:05 -0700 (Wed, 09 Aug 2017) | 20 lines

ARM: Fix CMP_SWAP expansion

Clean up after my misguided attempt in r304267 to "fix" CMP_SWAP
returning an uninitialized status value.

- I was always using tMOVi8 to zero the status register which cannot
  encode higher register numbers and llvm would silently miscompile)

- Nobody was ever looking at that status value outside the expansion.
  ARMDAGToDAGISel::SelectCMP_SWAP() the only place creating CMP_SWAP
  instructions was not mapping anything to it. (The cmpxchg status value
  from llvm IR is lowered to a manual comparison after the CMP_SWAP)

So this:
- Renames the register from "status" to "temp" it make it obvious that
  it isn't used outside the expansion.
- Remove the zeroing status/temp register.
- Keep the live-in list improvements from r304267

Fixes http://llvm.org/PR34056
------------------------------------------------------------------------
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/branches/release_50llvm.src
The file was modified/llvm/branches/release_50/lib/Target/ARM/ARMExpandPseudoInsts.cppllvm.src/lib/Target/ARM/ARMExpandPseudoInsts.cpp
The file was modified/llvm/branches/release_50/lib/Target/ARM/ARMInstrInfo.tdllvm.src/lib/Target/ARM/ARMInstrInfo.td
The file was modified/llvm/branches/release_50/test/CodeGen/ARM/cmpxchg-O0.llllvm.src/test/CodeGen/ARM/cmpxchg-O0.ll