SuccessChanges

Changes from Git (git http://labmaster3.local/git/llvm-project.git)

Summary

  1. AMDGPU: Slightly restructure m0 init code (details)
  2. AMDGPU: Stop adding m0 implicit def to SGPR spills (details)
  3. AMDGPU: Erase redundant redefs of m0 in SIFoldOperands (details)
  4. AMDGPU: Use CopyToReg for interp intrinsic lowering (details)
Commit b5234b64af83cb607e358eb77555f7f30ec0ced4 by Matthew.Arsenault
AMDGPU: Slightly restructure m0 init code
This will allow using another operation to produce the glue in a future
change.
llvm-svn: 375447
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
Commit dd6cf159bab7cfa5dd61670d5048dab48c934eba by Matthew.Arsenault
AMDGPU: Stop adding m0 implicit def to SGPR spills
r375293 removed the SGPR spilling with scalar stores path, so this is no
longer necessary. This also always had the defect of adding the def even
when this path wasn't in use.
llvm-svn: 375448
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/indirect-addressing-term.ll
Commit 8ebbf25cb1e9b2c95903917b2aa72363e5b20a42 by Matthew.Arsenault
AMDGPU: Erase redundant redefs of m0 in SIFoldOperands
Only handle simple inter-block redefs of m0 to the same value. This
avoids interference from redefs of m0 in SILoadStoreOptimzer. I was
initially teaching that pass to ignore redefs of m0, but having them not
exist beforehand is much simpler.
This is in preparation for deleting the current special m0 handling in
SIFixSGPRCopies to allow the register coalescer to handle the difficult
cases.
llvm-svn: 375449
The file was addedllvm/test/CodeGen/AMDGPU/fold-operands-remove-m0-redef.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIFoldOperands.cpp
Commit 38038f116f7b948a700e0edc4d3687c7b7fda926 by Matthew.Arsenault
AMDGPU: Use CopyToReg for interp intrinsic lowering
This doesn't use the default value, so doesn't benefit from the hack to
help optimize it.
llvm-svn: 375450
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.f16.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp