FailedChanges

Summary

  1. [TableGen] Fix a bug that MCSchedClassDesc is interfered between (details)
Commit bb8d54001075ed22fc63d366e33c3fcdfa3fd3e0 by qshanz
[TableGen] Fix a bug that MCSchedClassDesc is interfered between
different SchedModel
Assume that, ModelA has scheduling resource for InstA and ModelB has
scheduling resource for InstB. This is what the llvm::MCSchedClassDesc
looks like:
llvm::MCSchedClassDesc ModelASchedClasses[] = {
... InstA, 0, ... InstB, -1,...
};
llvm::MCSchedClassDesc ModelBSchedClasses[] = {
... InstA, -1,... InstB, 0,...
}; The -1 means invalid num of macro ops, while it is valid if it is
>=0. This is what we look like now:
llvm::MCSchedClassDesc ModelASchedClasses[] = {
... InstA, 0, ... InstB, 0,...
};
llvm::MCSchedClassDesc ModelBSchedClasses[] = {
... InstA, 0,... InstB, 0,...
}; And compiler hit the assertion here because the SCDesc is valid now
for both InstA and InstB.
Differential Revision: https://reviews.llvm.org/D67950
llvm-svn: 374524
The file was modifiedllvm/test/CodeGen/ARM/ParallelDSP/unroll-n-jam-smlad.ll
The file was addedllvm/test/TableGen/InvalidMCSchedClassDesc.td
The file was modifiedllvm/utils/TableGen/SubtargetEmitter.cpp