FailedChanges

Summary

  1. [AMDGPU] Come back patch for the 'Assign register class for cross block (details)
  2. Revert "Add a pass to lower is.constant and objectsize intrinsics" (details)
  3. DWARFExpression: Fix/add support for (v4) debug_loc base address (details)
  4. [DebugInfo] Fix truncation of call site immediates (details)
  5. [llvm-size] Tidy up error messages (PR42970) (details)
  6. [AArch64] Stackframe accesses to SVE objects. (details)
  7. [Alignment][NFC] Move and type functions from MathExtras to Alignment (details)
Commit c4d256a59049d4b2f21da83f43b9caba2427885e by Alexander.Timofeev
[AMDGPU] Come back patch for the 'Assign register class for cross block
values according to the divergence.'
  Detailed description:
    After https://reviews.llvm.org/D59990 submit several issues were
discovered.
   Changes in common code were preserved but AMDGPU specific part was
reverted to keep the backend working correctly.
    Discovered issues were addressed in the following commits:
    https://reviews.llvm.org/D67662
   https://reviews.llvm.org/D67101
   https://reviews.llvm.org/D63953
   https://reviews.llvm.org/D63731
    This change brings back AMDGPU specific changes.
  Reviewed by: rampitec, arsenm
  Differential Revision: https://reviews.llvm.org/D68635
llvm-svn: 374767
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.qsad.pk.u16.u8.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmed3.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.mov.dpp.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/use-sgpr-multiple-times.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/branch-uniformity.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/wave32.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.h
The file was modifiedllvm/test/CodeGen/AMDGPU/uniform-loop-inside-nonuniform.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/valu-i1.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/sgpr-copy.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/si-fix-sgpr-copies.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/smrd.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/fdiv32-to-rcp-folding.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.mqsad.pk.u16.u8.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/multilevel-break.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/fneg.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/si-annotate-cf.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/buffer-intrinsics-mmo-offsets.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/sgpr-control-flow.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/atomicrmw-nand.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/i1-copy-from-loop.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/fsub.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/i1-copy-phi-uniform-branch.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/madak.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/commute-shifts.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/select-opt.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/branch-relaxation.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/fabs.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/loop_break.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot-compute.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/copy-illegal-type.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.scale.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/cse-phi-incoming-val.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/fmin_legacy.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/fneg-fabs.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/implicit-def-muse.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/extract_subvector_vec4_vec3.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.cpp
Commit 1a21f98ac3c57d027908000b8bac356daec51416 by gribozavr
Revert "Add a pass to lower is.constant and objectsize intrinsics"
This reverts commit r374743. It broke the build with Ocaml enabled:
http://lab.llvm.org:8011/builders/clang-x86_64-debian-fast/builds/19218
llvm-svn: 374768
The file was modifiedllvm/bindings/ocaml/transforms/scalar_opts/llvm_scalar_opts.mli
The file was removedllvm/test/Transforms/LowerConstantIntrinsics/crash-on-large-allocas.ll
The file was removedllvm/test/Transforms/LowerConstantIntrinsics/objectsize_basic.ll
The file was modifiedllvm/lib/CodeGen/TargetPassConfig.cpp
The file was modifiedllvm/lib/Transforms/Scalar/Scalar.cpp
The file was modifiedllvm/test/Other/opt-Os-pipeline.ll
The file was removedllvm/test/Transforms/LowerConstantIntrinsics/constant-intrinsics.ll
The file was modifiedllvm/lib/Transforms/IPO/PassManagerBuilder.cpp
The file was modifiedllvm/test/CodeGen/AArch64/O3-pipeline.ll
The file was addedllvm/test/CodeGen/X86/is-constant.ll
The file was addedllvm/test/Transforms/CodeGenPrepare/basic.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
The file was modifiedllvm/include/llvm-c/Transforms/Scalar.h
The file was modifiedllvm/lib/Passes/PassBuilder.cpp
The file was modifiedllvm/include/llvm/Transforms/Scalar.h
The file was modifiedllvm/lib/CodeGen/CodeGenPrepare.cpp
The file was addedllvm/test/CodeGen/X86/object-size.ll
The file was addedllvm/test/Transforms/CodeGenPrepare/crash-on-large-allocas.ll
The file was addedllvm/test/CodeGen/Generic/is-constant.ll
The file was modifiedllvm/test/CodeGen/X86/O0-pipeline.ll
The file was addedllvm/test/Transforms/CodeGenPrepare/builtin-condition.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/FastISel.cpp
The file was modifiedllvm/test/Other/opt-O3-pipeline.ll
The file was modifiedllvm/test/CodeGen/AArch64/O0-pipeline.ll
The file was modifiedllvm/test/Other/new-pm-thinlto-defaults.ll
The file was modifiedllvm/bindings/ocaml/transforms/scalar_opts/scalar_opts_ocaml.c
The file was modifiedllvm/test/Other/opt-O2-pipeline.ll
The file was modifiedllvm/test/CodeGen/X86/O3-pipeline.ll
The file was modifiedllvm/lib/Passes/PassRegistry.def
The file was modifiedllvm/lib/Transforms/Scalar/CMakeLists.txt
The file was removedllvm/include/llvm/Transforms/Scalar/LowerConstantIntrinsics.h
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
The file was modifiedllvm/test/Other/new-pm-defaults.ll
The file was modifiedllvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
The file was modifiedllvm/test/Transforms/CodeGenPrepare/X86/overflow-intrinsics.ll
The file was modifiedllvm/include/llvm/InitializePasses.h
The file was modifiedllvm/utils/gn/secondary/llvm/lib/Transforms/Scalar/BUILD.gn
The file was modifiedllvm/test/CodeGen/ARM/O3-pipeline.ll
The file was removedllvm/lib/Transforms/Scalar/LowerConstantIntrinsics.cpp
The file was modifiedllvm/include/llvm/LinkAllPasses.h
Commit 5a8db8496440b9d6ced91bd24f4b6b463acc7d55 by pavel
DWARFExpression: Fix/add support for (v4) debug_loc base address
selection entries
The DWARFExpression is parsing the location lists in about five places.
Of those, only one actually had proper support for base address
selection entries.
Since r374600, llvm has started to produce location expressions with
base address selection entries more aggresively, which caused some tests
to fail.
This patch adds support for these entries to the places which had it
missing, fixing the failing tests. It also adds a targeted test for the
two of the three fixes, which should continue testing this functionality
even if the llvm output changes. I am not aware of a way to write a
targeted test for the third fix (DWARFExpression::Evaluate).
llvm-svn: 374769
The file was modifiedlldb/source/Expression/DWARFExpression.cpp
The file was modifiedlldb/test/Shell/SymbolFile/DWARF/debug_loc.s
Commit 8535bed79504ffe3ed7f2de8c158a17e79e54736 by david.stenberg
[DebugInfo] Fix truncation of call site immediates
Summary: This addresses a bug in collectCallSiteParameters() where call
site immediates would be truncated from int64_t to unsigned.
This fixes PR43525.
Reviewers: djtodoro, NikolaPrica, aprantl, vsk
Reviewed By: aprantl
Subscribers: hiraditya, llvm-commits
Tags: #debug-info, #llvm
Differential Revision: https://reviews.llvm.org/D68869
llvm-svn: 374770
The file was modifiedllvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
The file was addedllvm/test/DebugInfo/X86/dbgcall-site-64-bit-imms.ll
Commit 83e52f5e1150018329b8907bb014c77ac382d611 by maskray
[llvm-size] Tidy up error messages (PR42970)
Clean up some formatting inconsistencies in the error messages and
correctly exit with non-zero in all error cases.
Differential Revision: https://reviews.llvm.org/D68906 Patch by Alex
Cameron
llvm-svn: 374771
The file was modifiedllvm/tools/llvm-size/llvm-size.cpp
The file was modifiedllvm/test/tools/llvm-size/no-input.test
The file was modifiedllvm/test/tools/llvm-size/invalid-input.test
Commit 77748129650271ebd7b3f9c2c6c4f8110cb4a845 by sander.desmalen
[AArch64] Stackframe accesses to SVE objects.
Materialize accesses to SVE frame objects from SP or FP, whichever is
available and beneficial.
This patch still assumes the objects are pre-allocated. The automatic
layout of SVE objects within the stackframe will be added in a separate
patch.
Reviewers: greened, cameron.mcinally, efriedma, rengolin, thegameg,
rovka
Reviewed By: cameron.mcinally
Differential Revision: https://reviews.llvm.org/D67749
llvm-svn: 374772
The file was modifiedllvm/lib/Target/AArch64/AArch64FrameLowering.h
The file was modifiedllvm/lib/Target/AArch64/AArch64FrameLowering.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.cpp
The file was modifiedllvm/test/CodeGen/AArch64/framelayout-sve.mir
Commit ce56e1a1cc5714f4af5675dd963cfebed766d9e1 by gchatelet
[Alignment][NFC] Move and type functions from MathExtras to Alignment
Summary: This is patch is part of a series to introduce an Alignment
type. See this thread for context:
http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this
patch for the introduction of the type: https://reviews.llvm.org/D64790
Reviewers: courbet
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D68942
llvm-svn: 374773
The file was modifiedllvm/include/llvm/Support/MathExtras.h
The file was modifiedllvm/unittests/Support/TrailingObjectsTest.cpp
The file was modifiedllvm/lib/ProfileData/Coverage/CoverageMappingReader.cpp
The file was modifiedllvm/unittests/Support/AlignmentTest.cpp
The file was modifiedllvm/include/llvm/Support/TrailingObjects.h
The file was modifiedllvm/include/llvm/Support/Allocator.h
The file was modifiedllvm/include/llvm/Support/BinaryStreamReader.h
The file was modifiedllvm/include/llvm/Support/Alignment.h
The file was modifiedllvm/include/llvm/Support/BinaryStreamArray.h
The file was modifiedllvm/unittests/Support/AllocatorTest.cpp
The file was modifiedllvm/lib/Support/Unix/Memory.inc