SuccessChanges

Summary

  1. [ThinLTO] Import virtual method with single implementation in hybrid (details)
  2. [Alignment][NFC] Use Align for TargetFrameLowering/Subtarget (details)
  3. [DAGCombine][ARM] Enable extending masked loads (details)
Commit 943afb57aa65b03b29808765c4c657f03d3d0e94 by eleviant
[ThinLTO] Import virtual method with single implementation in hybrid
mode
Differential revision: https://reviews.llvm.org/D68782
llvm-svn: 375083
The file was addedllvm/test/ThinLTO/X86/Inputs/devirt_single_hybrid_bar.ll
The file was addedllvm/test/ThinLTO/X86/devirt_single_hybrid.ll
The file was modifiedllvm/lib/Transforms/IPO/WholeProgramDevirt.cpp
The file was addedllvm/test/ThinLTO/X86/Inputs/devirt_single_hybrid_foo.ll
Commit 882c43d703cd63889a5541bf8f2c014733cbbbee by gchatelet
[Alignment][NFC] Use Align for TargetFrameLowering/Subtarget
Summary: This is patch is part of a series to introduce an Alignment
type. See this thread for context:
http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this
patch for the introduction of the type: https://reviews.llvm.org/D64790
Reviewers: courbet
Subscribers: jholewinski, arsenm, dschuff, jyknight, dylanmckay,
sdardis, nemanjai, jvesely, nhaehnle, sbc100, jgravelle-google,
hiraditya, aheejin, kbarton, fedor.sergeev, asb, rbar, johnrusso,
simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng,
edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o,
PkmX, jocewei, jsji, Jim, lenary, s.egerton, pzheng, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D68993
llvm-svn: 375084
The file was modifiedllvm/lib/Target/BPF/BPFFrameLowering.h
The file was modifiedllvm/lib/Target/Lanai/LanaiFrameLowering.h
The file was modifiedllvm/lib/Target/AMDGPU/R600FrameLowering.h
The file was modifiedllvm/lib/Target/AMDGPU/SIFrameLowering.h
The file was modifiedllvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
The file was modifiedllvm/lib/Target/AVR/AVRFrameLowering.cpp
The file was modifiedllvm/lib/Target/Sparc/SparcFrameLowering.cpp
The file was modifiedllvm/lib/Target/Mips/MipsFrameLowering.h
The file was modifiedllvm/include/llvm/CodeGen/TargetFrameLowering.h
The file was modifiedllvm/lib/Target/XCore/XCoreFrameLowering.cpp
The file was modifiedllvm/lib/Target/ARC/ARCFrameLowering.h
The file was modifiedllvm/lib/Target/X86/X86Subtarget.h
The file was modifiedllvm/unittests/CodeGen/MachineInstrTest.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCSubtarget.h
The file was modifiedllvm/lib/Target/RISCV/RISCVFrameLowering.h
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
The file was modifiedllvm/lib/Target/Mips/MipsSubtarget.h
The file was modifiedllvm/lib/Target/X86/X86FrameLowering.cpp
The file was modifiedllvm/lib/Target/MSP430/MSP430FrameLowering.h
The file was modifiedllvm/lib/Target/NVPTX/NVPTXFrameLowering.cpp
The file was modifiedllvm/lib/Target/X86/X86TargetMachine.cpp
The file was modifiedllvm/lib/Target/X86/X86Subtarget.cpp
The file was modifiedllvm/lib/Target/Mips/MipsSubtarget.cpp
The file was modifiedllvm/lib/Target/Mips/MipsAsmPrinter.cpp
The file was modifiedllvm/lib/Target/Mips/MipsTargetMachine.cpp
The file was modifiedllvm/lib/Target/ARM/ARMSubtarget.h
The file was modifiedllvm/lib/Target/AArch64/AArch64FrameLowering.h
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUFrameLowering.cpp
The file was modifiedllvm/lib/Target/X86/X86FrameLowering.h
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyFrameLowering.h
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUFrameLowering.h
The file was modifiedllvm/lib/Target/PowerPC/PPCSubtarget.cpp
The file was modifiedllvm/lib/Target/ARM/ARMSubtarget.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonFrameLowering.h
Commit 39af8a3a3b666929752e6bdff0bd65fedbbc34e8 by sam.parker
[DAGCombine][ARM] Enable extending masked loads
Add generic DAG combine for extending masked loads.
Allow us to generate sext/zext masked loads which can access v4i8, v8i8
and v4i16 memory to produce v4i32, v8i16 and v4i32 respectively.
Differential Revision: https://reviews.llvm.org/D68337
llvm-svn: 375085
The file was modifiedllvm/test/CodeGen/Thumb2/mve-masked-store.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
The file was modifiedllvm/lib/Target/ARM/ARMInstrMVE.td
The file was modifiedllvm/test/Transforms/LoopVectorize/ARM/mve-maskedldst.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-tail-data-types.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-masked-ldst.ll
The file was modifiedllvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/Thumb2/mve-masked-load.ll