1. [ARM][MVE] Enable truncating masked stores (details)
  2. [AMDGPU] Improve code size cost model (details)
  3. [mips] [builtins] Remove clear_mips_cache Differential Revision: (details)
Commit 8e6a638c74dcc1587822df3b4a54214e2457410b by sam.parker
[ARM][MVE] Enable truncating masked stores
Allow us to generate truncating masked store which take v4i32 and v8i16
vectors and can store to v4i8, v4i16 and v8i8 and memory. Removed
support for unaligned masked stores.
Differential Revision:
llvm-svn: 375108
The file was modifiedllvm/test/CodeGen/Thumb2/mve-masked-store.ll
The file was modifiedllvm/lib/Target/ARM/
The file was modifiedllvm/lib/Target/ARM/ARMTargetTransformInfo.h
The file was modifiedllvm/test/CodeGen/Thumb2/mve-masked-ldst.ll
Commit 39720575117e5dff3c72b6bde3c44ea0f0940139 by daniil.fukalov
[AMDGPU] Improve code size cost model
Summary: Added estimation for zero size insertelement, extractelement
and llvm.fabs operators. Updated inline/unroll parameters default
Reviewers: rampitec, arsenm
Reviewed By: arsenm
Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr,
t-tye, hiraditya, llvm-commits
Tags: #llvm
Differential Revision:
llvm-svn: 375109
The file was modifiedllvm/test/Analysis/CostModel/AMDGPU/extractelement.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInline.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
The file was modifiedllvm/test/Analysis/CostModel/AMDGPU/fabs.ll
The file was modifiedllvm/test/Analysis/CostModel/AMDGPU/insertelement.ll
Commit 78c78cb5a12d31b016a91a8276a47664abee73df by zoran.jovanovic
[mips] [builtins] Remove clear_mips_cache Differential Revision:
llvm-svn: 375110
The file was modifiedcompiler-rt/lib/builtins/clear_cache.c