SuccessChanges

Summary

  1. [InstCombine] Pre-commit of test case showing miscompile bug in (details)
  2. [InstCombine] Fix miscompile bug in canEvaluateShuffled (details)
Commit 459134064daeef03a762979ab162587f94361cdc by bjorn.a.pettersson
[InstCombine] Pre-commit of test case showing miscompile bug in
canEvaluateShuffled
Adding the reproducer from  https://bugs.llvm.org/show_bug.cgi?id=43689,
showing that instcombine is doing a bad transform. It transforms
  %0 = insertelement <2 x i16> undef, i16 %a, i32 0
%1 = srem <2 x i16> %0, <i16 2, i16 1>
%2 = shufflevector <2 x i16> %1, <2 x i16> undef, <2 x i32> <i32 undef,
i32 0>
into
   %1 = insertelement <2 x i16> undef, i16 %a, i32 1
  %2 = srem <2 x i16> %1, <i16 undef, i16 2>
The undef denominator makes the whole srem undefined.
llvm-svn: 375207
The file was addedllvm/test/Transforms/InstCombine/shufflevector-div-rem.ll
Commit 6456252dbf67f26f88873e92c0813ebf8a1f96a3 by bjorn.a.pettersson
[InstCombine] Fix miscompile bug in canEvaluateShuffled
Summary: Add restrictions in canEvaluateShuffled to prevent that we for
example transform
  %0 = insertelement <2 x i16> undef, i16 %a, i32 0
%1 = srem <2 x i16> %0, <i16 2, i16 1>
%2 = shufflevector <2 x i16> %1, <2 x i16> undef, <2 x i32> <i32 undef,
i32 0>
into
   %1 = insertelement <2 x i16> undef, i16 %a, i32 1
  %2 = srem <2 x i16> %1, <i16 undef, i16 2>
as having an undef denominator makes the srem undefined (for all vector
elements).
Fixes: https://bugs.llvm.org/show_bug.cgi?id=43689
Reviewers: spatel, lebedev.ri
Reviewed By: spatel, lebedev.ri
Subscribers: lebedev.ri, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D69038
llvm-svn: 375208
The file was modifiedllvm/test/Transforms/InstCombine/shufflevector-div-rem.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp