SuccessChanges

Summary

  1. [MIParser] Set RegClassOrRegBank during instruction parsing (details)
Commit 95290827d7d01c63ac57b2cf5204215ba4ee4b06 by petar.avramovic
[MIParser] Set RegClassOrRegBank during instruction parsing
MachineRegisterInfo::createGenericVirtualRegister sets RegClassOrRegBank
to static_cast<RegisterBank *>(nullptr). MIParser on the other hand
doesn't. When we attempt to constrain Register Class on such VReg,
additional COPY is generated. This way we avoid COPY instructions
showing in test that have MIR input while they are not present with
llvm-ir input that was used to create given MIR for a -run-pass test.
Differential Revision: https://reviews.llvm.org/D68946
llvm-svn: 375502
The file was modifiedllvm/lib/CodeGen/MIRParser/MIParser.cpp
The file was modifiedllvm/test/CodeGen/MIR/Mips/setRegClassOrRegBank.mir
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/legalizer/add_vec_builtin.mir
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/legalizer/sitofp_and_uitofp.mir