SuccessChanges

Summary

  1. AMDGPU/GlobalISel: Legalize FDIV16 (details)
  2. [DAGCombiner] widen zext of popcount based on target support (details)
Commit c35b358b741b942aa89acb1fe0d22d4126287493 by Austin.Kerbow
AMDGPU/GlobalISel: Legalize FDIV16
Reviewers: arsenm
Reviewed By: arsenm
Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka,
dstuttard, tpr, t-tye, hiraditya, volkan, Petar.Avramovic, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D69347
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
The file was removedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fast-unsafe-fdiv.mir
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fdiv.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was modifiedllvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
Commit e6c145e0548e3b3de6eab27e44e1504387cf6b53 by spatel
[DAGCombiner] widen zext of popcount based on target support
zext (ctpop X) --> ctpop (zext X)
This is a prerequisite step for canonicalizing in the other direction
(narrow the popcount) in IR - PR43688:
https://bugs.llvm.org/show_bug.cgi?id=43688
I'm not sure if any other targets are affected, but I found a missing
fold for PPC, so added tests based on that. The reason we widen all the
way to 64-bit in these tests is because the initial DAG looks something
like this:
  t5: i8 = ctpop t4
t6: i32 = zero_extend t5  <-- created based on IR, but unused node?
   t7: i64 = zero_extend t5
Differential Revision: https://reviews.llvm.org/D69127
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
The file was modifiedllvm/test/CodeGen/PowerPC/popcnt-zext.ll