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Summary

  1. [AMDGPU] Fix Vreg_1 PHI lowering in SILowerI1Copies. (details)
Commit e921ede54068b94702efcc1654dd0027c844012c by cdevadas
[AMDGPU] Fix Vreg_1 PHI lowering in SILowerI1Copies.
There is a minor flaw in the implementation of function lowerPhis. This
function replaces values of regclass Vreg_1 (boolean values) involved in
PHIs into an SGPR. Currently it iterates over the MBBs and performs an
inplace lowering of PHIs and fails to lower any incoming value that
itself is another PHI of Vreg_1 regclass. The failure occurs only when
the MBB where the incoming PHI value belongs is not visited/lowered yet.
To fix this problem, collect all Vreg_1 PHIs upfront and then perform
the lowering.
Differential Revision: https://reviews.llvm.org/D69182
The file was addedllvm/test/CodeGen/AMDGPU/i1_copy_phi_with_phi_incoming_value.mir
The file was modifiedllvm/lib/Target/AMDGPU/SILowerI1Copies.cpp