1. [Docs] Reflect the slow migration from guard to widenable condition (details)
  2. [SelectionDAG] Enable lowering unordered atomics loads w/LoadSDNode (and (details)
Commit e14f935ce2c9b65e137c16d2383299975f17f2d4 by listmail
[Docs] Reflect the slow migration from guard to widenable condition
which is currently in progress.
The file was modifiedllvm/docs/LangRef.rst
Commit 2460989eabb8adca4b7973aa23997b5ec832219b by listmail
[SelectionDAG] Enable lowering unordered atomics loads w/LoadSDNode (and
stores w/StoreSDNode) by default
Enable the new SelectionDAG representation for unordered loads and
stores introduced in r371441 by default.  As a reminder, the new
lowering changes the representation of an unordered atomic load from an
AtomicSDNode - which is essentially a black box which gets passed
through without combines messing with it - to a LoadSDNode w/a atomic
marker on the MMO. The later parallels the way we handle volatiles, and
I've audited the code to ensure that every location which checks one
checks the other.
This has been fairly heavily fuzzed, and I examined diffs in a
reasonable large corpus of assembly by hand, so I'm reasonable sure this
is correct for the common case.  Late in the review for this, it was
discovered that I hadn't correctly handled cases which could be
legalized into CAS operations.  This points out that there's a strong
bias in the IR of the frontend I'm working with towards only legal
atomics.  If there are problems with this patch, the most likely area
will be legalization.
Differential Revision:
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/atomic-non-integer.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
The file was modifiedllvm/test/CodeGen/X86/atomic-non-integer-fp128.ll
The file was modifiedllvm/test/CodeGen/X86/combineIncDecVector-crash.ll
The file was modifiedllvm/test/CodeGen/X86/atomic-unordered.ll