SuccessChanges

Summary

  1. [mips] Implement Octeon+ `saa` and `saad` instructions (details)
  2. [mips] Support `octeon+` CPU in the `.set arch=` directive (details)
  3. [mips] Write `AFL_EXT_OCTEONP` flag to the `.MIPS.abiflags` section (details)
  4. [mips] Add `octeon+` to the list of CPUs accepted by the driver (details)
  5. [mips] Set macros for Octeon+ CPU (details)
  6. [NFC][CVP] Add some tests for `sub` with preexisting no-wrap flags (details)
Commit 7bed381eae12277d6e0ef7e8a56491d11589ee7f by simon
[mips] Implement Octeon+ `saa` and `saad` instructions
`saa` and `saad` are 32-bit and 64-bit store atomic add instructions.
   memory[base] = memory[base] + rt
These instructions are available for "Octeon+" CPU. The patch adds
support for both instructions to MIPS assembler and diassembler and
introduces new CPU type - "octeon+".
Next patches will implement `.set arch=octeon+` directive and
`AFL_EXT_OCTEONP` ISA extension flag support.
Differential Revision: https://reviews.llvm.org/D69849
The file was modifiedllvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
The file was addedllvm/test/MC/Mips/macro-saad.s
The file was modifiedllvm/lib/Target/Mips/MipsInstrInfo.td
The file was modifiedllvm/lib/Target/Mips/MipsSubtarget.h
The file was addedllvm/test/MC/Mips/cnmipsp/invalid.s
The file was addedllvm/test/MC/Disassembler/Mips/octeonp/valid.txt
The file was modifiedllvm/lib/Target/Mips/MipsScheduleGeneric.td
The file was modifiedllvm/lib/Target/Mips/MipsInstrFormats.td
The file was modifiedllvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
The file was addedllvm/test/MC/Disassembler/Mips/octeonp/valid-el.txt
The file was modifiedllvm/lib/Target/Mips/Mips.td
The file was modifiedllvm/test/MC/Mips/elf_eflags.s
The file was modifiedllvm/test/MC/Mips/elf_header.s
The file was addedllvm/test/MC/Mips/macro-saa.s
The file was modifiedllvm/lib/Target/Mips/MipsSubtarget.cpp
The file was addedllvm/test/MC/Mips/cnmipsp/valid.s
The file was modifiedllvm/lib/Target/Mips/Mips64InstrInfo.td
The file was modifiedllvm/lib/Target/Mips/MipsScheduleP5600.td
Commit 3718102d40d60ba415ac2b2b1108e411838838a5 by simon
[mips] Support `octeon+` CPU in the `.set arch=` directive
Differential Revision: https://reviews.llvm.org/D69850
The file was modifiedllvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
The file was modifiedllvm/test/MC/Mips/set-arch.s
Commit bf996f761b99108c71efc84688597b7c3c63139e by simon
[mips] Write `AFL_EXT_OCTEONP` flag to the `.MIPS.abiflags` section
Differential Revision: https://reviews.llvm.org/D69851
The file was modifiedllvm/test/MC/Mips/mips_abi_flags_xx.s
The file was modifiedllvm/lib/Target/Mips/MCTargetDesc/MipsABIFlagsSection.h
Commit 3552d3e0f7c943c3547c0227ddd80fd4d0732a7e by simon
[mips] Add `octeon+` to the list of CPUs accepted by the driver
The file was modifiedclang/lib/Basic/Targets/Mips.h
The file was modifiedclang/lib/Basic/Targets/Mips.cpp
The file was modifiedclang/test/Driver/mips-abi.c
The file was modifiedclang/test/Driver/mips-as.c
The file was modifiedclang/test/Misc/target-invalid-cpu-note.c
The file was modifiedclang/lib/Driver/ToolChains/Gnu.cpp
Commit a751f557d824c569a96051ea5feef1ff32bb4723 by simon
[mips] Set macros for Octeon+ CPU
The file was modifiedclang/lib/Basic/Targets/Mips.cpp
The file was modifiedclang/test/Preprocessor/init.c
Commit 55b445150da9101fda07a4c28ee6a4e4bc9fc89a by lebedev.ri
[NFC][CVP] Add some tests for `sub` with preexisting no-wrap flags
We can use those to further limit the ranges in LVI.
The file was modifiedllvm/test/Transforms/CorrelatedValuePropagation/icmp.ll