SuccessChanges

Summary

  1. Revert "[InstCombine] avoid crash from deleting an instruction that (details)
  2. [InstCombine] Add a test case for suboptimal handling of (double (details)
  3. [InstCombine] Turn (extractelement <1 x i64/double> (bitcast (x86_mmx))) (details)
  4. Revert "Fixed a profdata file size detection on Windows system." (details)
  5. [DirectedGraph]: Add setTargetNode member function Summary:Add the (details)
  6. [NFC] Add one test to verify the dependency brings by Macro-Fusion. (details)
  7. libc++ status page: New papers and issues adopted in Belfast (details)
  8. [clangd] Fixes colon escaping on Windows (details)
  9. [yaml2obj] - Add a way to describe the custom data that is not part of (details)
  10. [AArch64][SVE] Spilling/filling of SVE callee-saves. (details)
  11. [FixBB] - An attemp to fix clang-armv7-linux-build-cache builder. (details)
  12. Use MCRegister in copyPhysReg (details)
  13. [FixBB] - Fix one more std::min -> std::min<uint64_t> to make BB happy. (details)
  14. [TargetLowering][DAGCombine][MSP430] Shift Amount Threshold in (details)
Commit d115b9fd4a4b87c01db34dca99db434867b98976 by spatel
Revert "[InstCombine] avoid crash from deleting an instruction that
still has uses (PR43723) (2nd try)"
This reverts commit 56b2aee1875a1ee47ddf859a6584f8728787fb7b. Still
causes a use-after-free on sanitizer bots.
The file was modifiedllvm/test/Transforms/InstCombine/builtin-object-size-ptr.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstructionCombining.cpp
Commit d37db750c25dc3a7da66c97d973f7a64b7bf907b by craig.topper
[InstCombine] Add a test case for suboptimal handling of (double
(bitcast (<1 x i64> (bitcast (x86_mmx)))))
The outer bitcast gets turned into an extractelement and another bitcast
rather than combining away to a single bitcast from mmx to double.
The file was modifiedllvm/test/Transforms/InstCombine/bitcast-vec-canon.ll
Commit aafde063aaf09285c701c80cd4b543c2beb523e8 by craig.topper
[InstCombine] Turn (extractelement <1 x i64/double> (bitcast (x86_mmx)))
into a single bitcast from x86_mmx to i64/double.
The _m64 type is represented in IR as <1 x i64>. The x86-64 ABI on Linux
passes <1 x i64> as a double. MMX intrinsics use x86_mmx type in
IR.These things result in a lot of bitcasts in mmx code. There's another
instcombine that tries to turn bitcast <1 x i64> to double into
extractelement and a bitcast.
The combine here tries to reverse this extractelement conversion if we
see an mmx type.
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp
The file was modifiedllvm/test/Transforms/InstCombine/bitcast-vec-canon.ll
Commit 3d3445e3e691a34a72643d07e675c618adeddafc by vvereschaka
Revert "Fixed a profdata file size detection on Windows system."
This reverts commit bcbb121ff6c8440382abfce8f2911a095f14602b.
Using 'ls -o' is not compatible way to fix the problem. FreeBSD and OSX
version of 'ls' do not support -o flag and test gets failed on these
platforms.
Differential Revision: https://reviews.llvm.org/D69317
The file was modifiedllvm/test/tools/llvm-profdata/show-prof-size.test
Commit 6ef63638cb8bac243e0e59cec66a19c57b79e351 by whitneyt
[DirectedGraph]: Add setTargetNode member function Summary:Add the
setTargetNode member function to class DGEdge. Authored By:etiotto
Reviewer:bmahjour, Whitney, jdoerfert, Meinersbur, fhahn, kbarton,
dmgreen Reviewed By:Meinersbur Subscribers:dexonsmith, kristina,
llvm-commits Tag:LLVM Differential
Revision:https://reviews.llvm.org/D68474
The file was modifiedllvm/include/llvm/ADT/DirectedGraph.h
Commit af5df83671bc4d94bddf33381430b6291d95a4fc by 48825004
[NFC] Add one test to verify the dependency brings by Macro-Fusion.
The file was addedllvm/test/CodeGen/AArch64/macro-fusion.ll
Commit 2f4fb200b6befeb4ff884d5dc46c66ce3ffd9bfc by marshall
libc++ status page: New papers and issues adopted in Belfast
The file was modifiedlibcxx/www/cxx2a_status.html
Commit b4f46a9bb42972e663f8b7b4d15e4c8ed3fecef4 by ibiryukov
[clangd] Fixes colon escaping on Windows
vscode always escapes the colon on the file uri, which causes the
semantic highlighting fails on windows.
fixes: https://github.com/clangd/clangd/issues/176
The file was modifiedclang-tools-extra/clangd/clients/clangd-vscode/src/semantic-highlighting.ts
The file was modifiedclang-tools-extra/clangd/clients/clangd-vscode/package-lock.json
The file was modifiedclang-tools-extra/clangd/clients/clangd-vscode/package.json
Commit 06456daa9e59ffddc634e4f1aa592161653fbd36 by grimar
[yaml2obj] - Add a way to describe the custom data that is not part of
an output section.
Currently there is no way to describe the data that is not a part of an
output section. It can be a data used to align sections or to fill the
gaps with something, or another kind of custom data. In this patch I
suggest a way to describe it. It looks like that:
``` Sections:
- Type:    CustomFiller
   Pattern: "CCDD"
   Size:    4
- Name:    .bar
   Type:    SHT_PROGBITS
   Content: "FF"
```
I.e. I've added a kind of synthetic section with a synthetic type
"CustomFiller". In the code it is called a "SyntheticFiller", which is
"a synthetic section which might be used to write the custom data around
regular output sections. It does not present in the sections header
table, but it might affect the output file size and program headers
produced. Think about it as about piece of data."
`SyntheticFiller` currently has a `Pattern` field and a `Size` field +
an optional `Name`. When written, `Size` of bytes in the output will be
filled with a `Pattern`. It is possible to reference a named filler it
by name from the program headers description, just like any other normal
section.
Differential revision: https://reviews.llvm.org/D69709
The file was modifiedllvm/tools/obj2yaml/elf2yaml.cpp
The file was modifiedllvm/lib/ObjectYAML/ELFYAML.cpp
The file was addedllvm/test/tools/yaml2obj/custom-fill.yaml
The file was modifiedllvm/include/llvm/ObjectYAML/ELFYAML.h
The file was modifiedllvm/test/tools/yaml2obj/program-header.yaml
The file was modifiedllvm/test/tools/yaml2obj/duplicate-section-names.test
The file was modifiedllvm/include/llvm/ObjectYAML/YAML.h
The file was modifiedllvm/lib/ObjectYAML/ELFEmitter.cpp
The file was modifiedllvm/lib/ObjectYAML/YAML.cpp
Commit 84a0c8e3ae92829c4f04ba995b4b6283d397f65d by sander.desmalen
[AArch64][SVE] Spilling/filling of SVE callee-saves.
Implement the spills/fills of callee-saved SVE registers using STR and
LDR instructions.
Also adds the `aarch64_sve_vector_pcs` attribute to specify the
callee-saved registers to be used for functions that return SVE vectors
or take SVE vectors as arguments. The callee-saved registers are vector
registers z8-z23 and predicate registers p4-p15.
The overal frame-layout with SVE will be as follows:
   +-------------+
  | stack args  |
  +-------------+
  | Callee Saves|
  |   X29, X30  |
  |-------------| <- FP
  | SVE Callee  | < //////////////
  | saved regs  | < //////////////
  |    z23      | < //////////////
  |     :       | < // SCALABLE //
  |    z8       | < //////////////
  |    p15      | < /// STACK ////
  |     :       | < //////////////
  |    p4       | < //// AREA ////
  +-------------+ < //////////////
  |     :       | < //////////////
  |  SVE locals | < //////////////
  |     :       | < //////////////
  +-------------+
  |/////////////| alignment gap.
  |     :       |
  | Stack objs  |
  |     :       |
  +-------------+ <- SP after call and frame-setup
Reviewers: cameron.mcinally, efriedma, greened, thegameg, ostannard,
rengolin
Reviewed By: ostannard
Differential Revision: https://reviews.llvm.org/D68996
The file was modifiedllvm/lib/AsmParser/LLParser.cpp
The file was modifiedllvm/lib/IR/AsmWriter.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64FrameLowering.h
The file was modifiedllvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h
The file was modifiedllvm/lib/Target/AArch64/AArch64FrameLowering.cpp
The file was modifiedllvm/lib/AsmParser/LLLexer.cpp
The file was modifiedllvm/lib/AsmParser/LLToken.h
The file was modifiedllvm/lib/Target/AArch64/AArch64CallingConvention.td
The file was modifiedllvm/test/CodeGen/AArch64/framelayout-sve.mir
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
Commit a26d7b629823bfb502d65e10c75e78754c5970d2 by grimar
[FixBB] - An attemp to fix clang-armv7-linux-build-cache builder.
http://lab.llvm.org:8011/builders/clang-armv7-linux-build-cache/builds/22130/steps/build%20stage%201/logs/stdio
/usr/bin/c++   -DGTEST_HAS_RTTI=0 -D_DEBUG -D_FILE_OFFSET_BITS=64
-D_GNU_SOURCE -D_LARGEFILE_SOURCE -D__STDC_CONSTANT_MACROS
-D__STDC_FORMAT_MACROS -D__STDC_LIMIT_MACROS -Ilib/ObjectYAML
-I/home/buildslave/buildslave/clang-armv7-linux-build-cache/llvm/llvm/lib/ObjectYAML
-I/usr/include/libxml2 -Iinclude
-I/home/buildslave/buildslave/clang-armv7-linux-build-cache/llvm/llvm/include
-mthumb -fPIC -fvisibility-inlines-hidden -Werror=date-time
-Werror=unguarded-availability-new -Wall -Wextra -Wno-unused-parameter
-Wwrite-strings -Wcast-qual -Wmissing-field-initializers -pedantic
-Wno-long-long -Wimplicit-fallthrough -Wcovered-switch-default
-Wno-noexcept-type -Wnon-virtual-dtor -Wdelete-non-virtual-dtor
-Wstring-conversion -fdiagnostics-color -ffunction-sections
-fdata-sections -O3    -UNDEBUG  -fno-exceptions -fno-rtti -std=c++14
-MMD -MT lib/ObjectYAML/CMakeFiles/LLVMObjectYAML.dir/YAML.cpp.o -MF
lib/ObjectYAML/CMakeFiles/LLVMObjectYAML.dir/YAML.cpp.o.d -o
lib/ObjectYAML/CMakeFiles/LLVMObjectYAML.dir/YAML.cpp.o -c
/home/buildslave/buildslave/clang-armv7-linux-build-cache/llvm/llvm/lib/ObjectYAML/YAML.cpp
/home/buildslave/buildslave/clang-armv7-linux-build-cache/llvm/llvm/lib/ObjectYAML/YAML.cpp:42:41:
error: no matching function for call to 'min'
   OS.write((const char *)Data.data(), std::min(N, Data.size()));
                                       ^~~~~~~~
/usr/bin/../lib/gcc/arm-linux-gnueabihf/5.4.0/../../../../include/c++/5.4.0/bits/algorithmfwd.h:370:5:
note: candidate template ignored: deduced conflicting types for
parameter '_Tp' ('unsigned long long' vs. 'unsigned int')
   min(const _Tp&, const _Tp&);
   ^
/usr/bin/../lib/gcc/arm-linux-gnueabihf/5.4.0/../../../../include/c++/5.4.0/bits/stl_algo.h:3451:5:
note: candidate template ignored: could not match
'initializer_list<type-parameter-0-0>' against 'unsigned long long'
   min(initializer_list<_Tp> __l, _Compare __comp)
   ^
/usr/bin/../lib/gcc/arm-linux-gnueabihf/5.4.0/../../../../include/c++/5.4.0/bits/algorithmfwd.h:375:5:
note: candidate function template not viable: requires 3 arguments, but
2 were provided
   min(const _Tp&, const _Tp&, _Compare);
   ^
/usr/bin/../lib/gcc/arm-linux-gnueabihf/5.4.0/../../../../include/c++/5.4.0/bits/stl_algo.h:3445:5:
note: candidate function template not viable: requires single argument
'__l', but 2 arguments were provided
   min(initializer_list<_Tp> __l)
   ^
/home/buildslave/buildslave/clang-armv7-linux-build-cache/llvm/llvm/lib/ObjectYAML/YAML.cpp:46:28:
error: no matching function for call to 'min'
for (uint64_t I = 0, E = std::min(N, Data.size() / 2); I != E; ++I) {
                          ^~~~~~~~
/usr/bin/../lib/gcc/arm-linux-gnueabihf/5.4.0/../../../../include/c++/5.4.0/bits/algorithmfwd.h:370:5:
note: candidate template ignored: deduced conflicting types for
parameter '_Tp' ('unsigned long long' vs. 'unsigned int')
   min(const _Tp&, const _Tp&);
   ^
/usr/bin/../lib/gcc/arm-linux-gnueabihf/5.4.0/../../../../include/c++/5.4.0/bits/stl_algo.h:3451:5:
note: candidate template ignored: could not match
'initializer_list<type-parameter-0-0>' against 'unsigned long long'
   min(initializer_list<_Tp> __l, _Compare __comp)
   ^
/usr/bin/../lib/gcc/arm-linux-gnueabihf/5.4.0/../../../../include/c++/5.4.0/bits/algorithmfwd.h:375:5:
note: candidate function template not viable: requires 3 arguments, but
2 were provided
   min(const _Tp&, const _Tp&, _Compare);
   ^
/usr/bin/../lib/gcc/arm-linux-gnueabihf/5.4.0/../../../../include/c++/5.4.0/bits/stl_algo.h:3445:5:
note: candidate function template not viable: requires single argument
'__l', but 2 arguments were provided
   min(initializer_list<_Tp> __l)
Fix: specify the type for std::min call.
The file was modifiedllvm/lib/ObjectYAML/YAML.cpp
Commit e6c9a9af398baf40537d45498e0aaf417c1306dc by arsenm2
Use MCRegister in copyPhysReg
The file was modifiedllvm/lib/Target/AMDGPU/R600InstrInfo.cpp
The file was modifiedllvm/lib/Target/Mips/Mips16InstrInfo.cpp
The file was modifiedllvm/lib/Target/XCore/XCoreInstrInfo.cpp
The file was modifiedllvm/lib/Target/AVR/AVRInstrInfo.h
The file was modifiedllvm/lib/Target/Mips/MipsSEInstrInfo.h
The file was modifiedllvm/lib/Target/Sparc/SparcInstrInfo.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
The file was modifiedllvm/lib/Target/BPF/BPFInstrInfo.cpp
The file was modifiedllvm/lib/Target/MSP430/MSP430InstrInfo.cpp
The file was modifiedllvm/lib/Target/Lanai/LanaiInstrInfo.cpp
The file was modifiedllvm/lib/Target/MSP430/MSP430InstrInfo.h
The file was modifiedllvm/lib/Target/Mips/MipsSEInstrInfo.cpp
The file was modifiedllvm/lib/Target/Lanai/LanaiInstrInfo.h
The file was modifiedllvm/lib/Target/Sparc/SparcInstrInfo.h
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.h
The file was modifiedllvm/lib/Target/ARC/ARCInstrInfo.cpp
The file was modifiedllvm/lib/Target/ARM/Thumb2InstrInfo.h
The file was modifiedllvm/lib/Target/ARM/Thumb2InstrInfo.cpp
The file was modifiedllvm/lib/Target/ARM/Thumb1InstrInfo.h
The file was modifiedllvm/include/llvm/CodeGen/TargetInstrInfo.h
The file was modifiedllvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp
The file was modifiedllvm/lib/Target/ARC/ARCInstrInfo.h
The file was modifiedllvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
The file was modifiedllvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrInfo.h
The file was modifiedllvm/lib/Target/ARM/ARMBaseInstrInfo.h
The file was modifiedllvm/lib/Target/NVPTX/NVPTXInstrInfo.h
The file was modifiedllvm/lib/Target/AVR/AVRInstrInfo.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfo.h
The file was modifiedllvm/lib/Target/SystemZ/SystemZInstrInfo.h
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.cpp
The file was modifiedllvm/lib/Target/X86/X86InstrInfo.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrInfo.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfo.cpp
The file was modifiedllvm/lib/Target/X86/X86InstrInfo.h
The file was modifiedllvm/lib/Target/Mips/Mips16InstrInfo.h
The file was modifiedllvm/lib/Target/BPF/BPFInstrInfo.h
The file was modifiedllvm/lib/Target/XCore/XCoreInstrInfo.h
The file was modifiedllvm/lib/Target/ARM/Thumb1InstrInfo.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.h
The file was modifiedllvm/lib/Target/AMDGPU/R600InstrInfo.h
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.h
The file was modifiedllvm/lib/Target/Hexagon/HexagonInstrInfo.h
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp
Commit 6b15c5dface2c70c9a17f80d3aa95af2c7658a7d by grimar
[FixBB] - Fix one more std::min -> std::min<uint64_t> to make BB happy.
BB:
http://lab.llvm.org:8011/builders/clang-armv7-linux-build-cache/builds/22133/steps/build%20stage%201/logs/stdio
The file was modifiedllvm/lib/ObjectYAML/YAML.cpp
Commit e0012c5d6acb568c77c7a6b845637f330e64515f by joan.lluch
[TargetLowering][DAGCombine][MSP430] Shift Amount Threshold in
DAGCombine (3)
Summary: Additional filtering of undesired shifts for targets that do
not support them efficiently.
Related with  D69116 and  D69120
Applies the TLI.getShiftAmountThreshold hook to prevent undesired
generation of shifts for the following IR code:
``` define i16 @testShiftBits(i16 %a) { entry:
%and = and i16 %a, -64
%cmp = icmp eq i16 %and, 64
%conv = zext i1 %cmp to i16
ret i16 %conv
}
define i16 @testShiftBits_11(i16 %a) { entry:
%cmp = icmp ugt i16 %a, 63
%conv = zext i1 %cmp to i16
ret i16 %conv
}
define i16 @testShiftBits_12(i16 %a) { entry:
%cmp = icmp ult i16 %a, 64
%conv = zext i1 %cmp to i16
ret i16 %conv
}
``` The attached diff file shows the piece code in TargetLowering that
is responsible for the generation of shifts in relation to the IR above.
Before applying this patch, shifts will be generated to replace
non-legal icmp immediates. However, shifts may be undesired if they are
even more expensive for the target.
For all my previous patches in this series (cited above) I added test
cases for the MSP430 target. However, in this case, the target is not
suitable for showing improvements related with this patch, because the
MSP430 does not implement "isLegalICmpImmediate". The default
implementation returns always true, therefore the patched code in
TargetLowering is never reached for that target. Targets implementing
both "isLegalICmpImmediate" and "getShiftAmountThreshold" will benefit
from this.
The differential effect of this patch can only be shown for the MSP430
by temporarily implementing "isLegalICmpImmediate" to return false for
large immediates. This is simulated with the implementation of a command
line flag that was incorporated in D69975
This patch belongs to a initiative to "relax" the generation of shifts
by LLVM for targets requiring it
Reviewers: spatel, lebedev.ri, asl
Reviewed By: spatel
Subscribers: lenary, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D69326
The file was modifiedllvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
The file was modifiedllvm/test/CodeGen/MSP430/shift-amount-threshold-b.ll