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Summary

  1. [RISCV] Use addi rather than add x0 (details)
Commit 32d840d29179383a28d59d68fccd74f52f316faf by selliott
[RISCV] Use addi rather than add x0
Summary: The RISC-V backend used to generate `add <reg>, x0, <reg>` in a
few instances. It seems most places no longer generate this sequence.
This is semantically equivalent to `addi <reg>, <reg>, 0`, but the
latter has the advantage of being noted to be the canonical instruction
to be used for moves (which microarchitectures can and should recognise
as such).
The changed testcases use instruction aliases - `mv <reg>, <reg>` is an
alias for `addi <reg>, <reg>, 0`.
Reviewers: luismarques
Reviewed By: luismarques
Subscribers: hiraditya, asb, rbar, johnrusso, simoncook, apazos,
sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng,
edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX,
jocewei, psnobl, benna, Jim, s.egerton, pzheng, sameer.abuasal,
llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D70124
The file was modifiedllvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
The file was modifiedllvm/test/CodeGen/RISCV/atomic-rmw.ll