SuccessChanges

Summary

  1. [ARM,MVE] Add intrinsics for 'administrative' vector operations. (details)
  2. [ARM,MVE] Add intrinsics for vector get/set lane. (details)
Commit 902e84556a51c70d95088aaa059ab9c494ab3516 by simon.tatham
[ARM,MVE] Add intrinsics for 'administrative' vector operations.
This batch of intrinsics includes lots of things that move vector data
around or change its type without really affecting its value very much.
It includes the `vreinterpretq` family (cast one vector type to
another); `vuninitializedq` (create a vector of a given type with
don't-care contents); and `vcreateq` (make a 128-bit vector out of two
`uint64_t` halves).
These are all implemented using completely standard IR that's already
tested in existing LLVM unit tests, so I've just written a clang test to
check the IR is correct, and left it at that.
I've also added some richer infrastructure to the MveEmitter Tablegen
backend, to make it specify the exact integer type of integer arguments
passed to IR construction functions, and wrap those arguments in a
`static_cast` in the autogenerated C++. That was necessary to prevent an
overloading ambiguity when passing the integer literal `0` to
`IRBuilder::CreateInsertElement`, because otherwise, it could mean
either a null pointer `llvm::Value *` or a zero `uint64_t`.
Reviewers: ostannard, MarkMurrayARM, dmgreen
Subscribers: kristof.beyls, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D70133
The file was modifiedclang/include/clang/Basic/arm_mve_defs.td
The file was addedclang/test/CodeGen/arm-mve-intrinsics/admin.c
The file was modifiedclang/include/clang/Basic/arm_mve.td
The file was modifiedclang/utils/TableGen/MveEmitter.cpp
Commit 9e37892773c0954a15f84b011223da1e707ab3bf by simon.tatham
[ARM,MVE] Add intrinsics for vector get/set lane.
This adds the `vgetq_lane` and `vsetq_lane` families, to copy between a
scalar and a specified lane of a vector.
One of the new `vgetq_lane` intrinsics returns a `float16_t`, which
causes a compile error if `%clang_cc1` doesn't get the option
`-fallow-half-arguments-and-returns`. The driver passes that option to
cc1 already, but I've had to edit all the explicit cc1 command lines in
the existing MVE intrinsics tests.
A couple of fixes are included for the code I wrote up front in
MveEmitter to support lane-index immediates (and which nothing has
tested until now): the type was wrong (`uint32_t` instead of `int`) and
the range was off by one.
I've also added a method of bypassing the default promotion to `i32`
that is done by the MveEmitter code generation: it's sensible to promote
short scalars like `i16` to `i32` if they're going to be passed to
custom IR intrinsics representing a machine instruction operating on
GPRs, but not if they're going to be passed to standard IR operations
like `insertelement` which expect the exact type.
Reviewers: ostannard, MarkMurrayARM, dmgreen
Reviewed By: dmgreen
Subscribers: kristof.beyls, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D70188
The file was modifiedclang/test/CodeGen/arm-mve-intrinsics/vldr.c
The file was modifiedclang/test/CodeGen/arm-mve-intrinsics/vadc.c
The file was modifiedclang/include/clang/Basic/arm_mve.td
The file was modifiedclang/test/CodeGen/arm-mve-intrinsics/load-store.c
The file was modifiedclang/test/CodeGen/arm-mve-intrinsics/scalar-shifts.c
The file was modifiedclang/test/CodeGen/arm-mve-intrinsics/vcvt.c
The file was modifiedclang/test/Sema/arm-mve-immediates.c
The file was modifiedclang/include/clang/Basic/arm_mve_defs.td
The file was modifiedclang/test/CodeGen/arm-mve-intrinsics/vld24.c
The file was addedclang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c
The file was modifiedclang/utils/TableGen/MveEmitter.cpp
The file was modifiedclang/test/CodeGen/arm-mve-intrinsics/scatter-gather.c
The file was modifiedclang/test/CodeGen/arm-mve-intrinsics/vaddq.c
The file was modifiedclang/test/CodeGen/arm-mve-intrinsics/vminvq.c