Revision
346742
by tstellar:
Merging r342946: ------------------------------------------------------------------------ r342946 | smaksimovic | 2018-09-24 23:27:49 -0700 (Mon, 24 Sep 2018) | 6 lines [mips] Correct MUL pattern for mips64 Guard existing pattern with a predicate, introduce a new one for revision 6. Differential Revision: https://reviews.llvm.org/D51684 ------------------------------------------------------------------------ |
| Change Type | Path in Repository | Path in Workspace |
|---|
 | /llvm/branches/release_70/lib/Target/Mips/Mips64InstrInfo.td (diff) | llvm.src/lib/Target/Mips/Mips64InstrInfo.td |
| /llvm/branches/release_70/lib/Target/Mips/Mips64r6InstrInfo.td (diff) | llvm.src/lib/Target/Mips/Mips64r6InstrInfo.td |
Revision
346741
by tstellar:
Merging r342884: ------------------------------------------------------------------------ r342884 | petarj | 2018-09-24 07:14:19 -0700 (Mon, 24 Sep 2018) | 12 lines [Mips][FastISel] Fix selectBranch on icmp i1 The r337288 tried to fix result of icmp i1 when its input is not sanitized by falling back to DagISel. While it now produces the correct result for bit 0, the other bits can still hold arbitrary value which is not supported by MipsFastISel branch lowering. This patch fixes the issue by falling back to DagISel in this case. Patch by Dragan Mladjenovic. Differential Revision: https://reviews.llvm.org/D52045 ------------------------------------------------------------------------ |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /llvm/branches/release_70/lib/Target/Mips/MipsFastISel.cpp (diff) | llvm.src/lib/Target/Mips/MipsFastISel.cpp |
 | /llvm/branches/release_70/test/CodeGen/Mips/Fast-ISel/bricmpi1.ll | llvm.src/test/CodeGen/Mips/Fast-ISel/bricmpi1.ll |
Revision
346739
by tstellar:
Merging r341919: ------------------------------------------------------------------------ r341919 | atanasyan | 2018-09-11 02:57:25 -0700 (Tue, 11 Sep 2018) | 18 lines [mips] Add a pattern for 64-bit GPR variant of the `rdhwr` instruction MIPS ISAs start to support third operand for the `rdhwr` instruction starting from Revision 6. But LLVM generates assembler code with three-operands version of this instruction on any MIPS64 ISA. The third operand is always zero, so in case of direct code generation we get correct code. This patch fixes the bug by adding an instruction alias. The same alias already exists for 32-bit ISA. Ideally, we also need to reject three-operands version of the `rdhwr` instruction in an assembler code if ISA revision is less than 6. That is a task for a separate patch. This fixes PR38861 (https://bugs.llvm.org/show_bug.cgi?id=38861) Differential revision: https://reviews.llvm.org/D51773 ------------------------------------------------------------------------ |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /llvm/branches/release_70/lib/Target/Mips/Mips64InstrInfo.td (diff) | llvm.src/lib/Target/Mips/Mips64InstrInfo.td |
| /llvm/branches/release_70/test/CodeGen/Mips/tls.ll (diff) | llvm.src/test/CodeGen/Mips/tls.ll |
Revision
346737
by tstellar:
Merging r341221: ------------------------------------------------------------------------ r341221 | atanasyan | 2018-08-31 08:57:17 -0700 (Fri, 31 Aug 2018) | 12 lines [mips] Fix `mtc1` and `mfc1` definitions for microMIPS R6 The `mtc1` and `mfc1` definitions in the MipsInstrFPU.td have MMRel, but do not have StdMMR6Rel tags. When these instructions are emitted for microMIPS R6 targets, `Mips::MipsR62MicroMipsR6` nor `Mips::Std2MicroMipsR6` cannot find correct op-codes and as a result the backend uses mips32 variant of the instructions encoding. The patch fixes this problem by adding the StdMMR6Rel tag and check instructions encoding in the test case. Differential revision: https://reviews.llvm.org/D51482 ------------------------------------------------------------------------ |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /llvm/branches/release_70/lib/Target/Mips/MicroMips32r6InstrInfo.td (diff) | llvm.src/lib/Target/Mips/MicroMips32r6InstrInfo.td |
| /llvm/branches/release_70/lib/Target/Mips/MipsInstrFPU.td (diff) | llvm.src/lib/Target/Mips/MipsInstrFPU.td |
| /llvm/branches/release_70/test/CodeGen/Mips/micromips-mtc-mfc.ll | llvm.src/test/CodeGen/Mips/micromips-mtc-mfc.ll |
Revision
346736
by tstellar:
Merging r340932: ------------------------------------------------------------------------ r340932 | atanasyan | 2018-08-29 07:54:01 -0700 (Wed, 29 Aug 2018) | 11 lines [mips] Fix microMIPS unconditional branch offset handling MipsSEInstrInfo class defines for internal purpose unconditional branches as Mips::B nad Mips:J even in case of microMIPS code generation. Under some conditions that leads to the bug - for rather long branch which fits to Mips jump instruction offset size, but does not fit to microMIPS jump offset size, we generate 'short' branch and later show an error 'out of range PC16 fixup' after check in the isBranchOffsetInRange routine. Differential revision: https://reviews.llvm.org/D50615 ------------------------------------------------------------------------ |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /llvm/branches/release_70/lib/Target/Mips/MipsSEInstrInfo.cpp (diff) | llvm.src/lib/Target/Mips/MipsSEInstrInfo.cpp |
| /llvm/branches/release_70/test/CodeGen/Mips/micromips-b-range.ll | llvm.src/test/CodeGen/Mips/micromips-b-range.ll |
Revision
346735
by tstellar:
Merging r340931: ------------------------------------------------------------------------ r340931 | atanasyan | 2018-08-29 07:53:55 -0700 (Wed, 29 Aug 2018) | 6 lines [mips] Involves microMIPS's jump in the analyzable branch set Involves microMIPS's jump in the analyzable branch set to reduce some code patterns. Differential revision: https://reviews.llvm.org/D50613 ------------------------------------------------------------------------ |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /llvm/branches/release_70/lib/Target/Mips/MipsSEInstrInfo.cpp (diff) | llvm.src/lib/Target/Mips/MipsSEInstrInfo.cpp |
| /llvm/branches/release_70/test/CodeGen/Mips/longbranch.ll (diff) | llvm.src/test/CodeGen/Mips/longbranch.ll |
Revision
346734
by tstellar:
Merging r340927: ------------------------------------------------------------------------ r340927 | vstefanovic | 2018-08-29 07:07:14 -0700 (Wed, 29 Aug 2018) | 14 lines [mips] Prevent shrink-wrap for BuildPairF64, ExtractElementF64 when they use $sp For a certain combination of options, BuildPairF64_{64}, ExtractElementF64{_64} may be expanded into instructions using stack. Add implicit operand $sp for such cases so that ShrinkWrapping doesn't move prologue setup below them. Fixes MultiSource/Benchmarks/MallocBench/cfrac for '--target=mips-img-linux-gnu -mcpu=mips32r6 -mfpxx -mnan=2008' and '--target=mips-img-linux-gnu -mcpu=mips32r6 -mfp64 -mnan=2008 -mno-odd-spreg'. Differential Revision: https://reviews.llvm.org/D50986 ------------------------------------------------------------------------ |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /llvm/branches/release_70/lib/Target/Mips/MipsSEFrameLowering.cpp (diff) | llvm.src/lib/Target/Mips/MipsSEFrameLowering.cpp |
| /llvm/branches/release_70/lib/Target/Mips/MipsSEISelDAGToDAG.cpp (diff) | llvm.src/lib/Target/Mips/MipsSEISelDAGToDAG.cpp |
| /llvm/branches/release_70/test/CodeGen/Mips/buildpairf64-extractelementf64-implicit-sp.ll | llvm.src/test/CodeGen/Mips/buildpairf64-extractelementf64-implicit-sp.ll |
| /llvm/branches/release_70/test/CodeGen/Mips/shrink-wrap-buildpairf64-extractelementf64.mir | llvm.src/test/CodeGen/Mips/shrink-wrap-buildpairf64-extractelementf64.mir |
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