FailedChanges

Changes from Git (git http://labmaster3.local/git/llvm-project.git)

Summary

  1. [SimplifyCFG] mergeConditionalStoreToAddress(): consider cost, not (details)
  2. [AArch64] Don't implicitly enable global isel on Darwin if (details)
  3. [InstCombine] foldUnsignedUnderflowCheck(): handle last few cases (details)
  4. [CodeGen][X86][NFC] Tests for (sub Carry, X) -> (addcarry (sub 0, X), 0, (details)
  5. [DAGCombine][ARM][X86] (sub Carry, X)  ->  (addcarry (sub 0, X), 0, (details)
  6. On PowerPC, Secure-PLT by default for FreeBSD 13 and higher (details)
  7. On PowerPC, Secure-PLT by default for FreeBSD 13 and higher (details)
  8. [SimplifyCFG] mergeConditionalStoreToAddress(): try to pacify MSAN (details)
  9. fix build, adjust test also for Windows path separator (details)
  10. llvm-reduce: Add pass to reduce basic blocks (details)
  11. gn build: Merge r372264 (details)
  12. [lld][WebAssembly] Fix use after free of archive path (details)
  13. Add AutoUpgrade function to add new address space datalayout string to (details)
  14. gn build: Merge r372267 (details)
  15. [analyzer] PR43102: Fix an assertion and an out-of-bounds error for (details)
  16. llvm-reduce: Fix inconsistencies between int/unsigned usage (standardize (details)
  17. llvm-reduce: Remove inaccurate doxy comment about a return that isn't (details)
  18. Remove the obsolete BlockByRefStruct flag from LLVM IR (details)
  19. [AArch64][GlobalISel] Support lowering musttail calls (details)
  20. [Docs] Moves topics to new categories (details)
  21. [WebAssembly] Restore defaults for stores per memop (details)
  22. [utils] Amend update_llc_test_checks.py to non-llc tooling, NFC (details)
  23. [utils] Add minimal support for MIR inputs to update_llc_test_checks.py (details)
  24. [Object] Extend MachOUniversalBinary::getObjectForArch (details)
  25. llvm-reduce: Avoid use-after-free when removing a branch instruction (details)
  26. Initialize all fields in ABIArgInfo. (details)
  27. llvm-reduce: Add pass to reduce instructions (details)
  28. gn build: Merge r372282 (details)
  29. [WebAssembly] Sort output data sections to place .bss last (details)
  30. GlobalISel: Don't materialize immarg arguments to intrinsics (details)
  31. AMDGPU/GlobalISel: Fix RegBankSelect G_SMULH/G_UMULH pre-gfx9 (details)
  32. MachineScheduler: Fix assert from not checking subregs (details)
  33. Fix typo (details)
  34. AMDGPU/GlobalISel: Attempt to RegBankSelect image intrinsics (details)
  35. AMDGPU/GlobalISel: RegBankSelect llvm.amdgcn.raw.buffer.{load|store} (details)
  36. AMDGPU/GlobalISel: RegBankSelect struct buffer load/store (details)
  37. AMDGPU/GlobalISel: Select llvm.amdgcn.raw.buffer.store (details)
  38. AMDGPU/GlobalISel: Select llvm.amdgcn.raw.buffer.store.format (details)
  39. [CLANG][BPF] change __builtin_preserve_access_index() signature (details)
  40. AMDGPU/GlobalISel: RegBankSelect tbuffer load/store (details)
  41. AMDGPU/GlobalISel: RegBankSelect llvm.amdgcn.ds.swizzle (details)
  42. AMDGPU/SILoadStoreOptimizer: Add const to more functions (details)
  43. [Builtins] Delete setjmp_syscall and qsetjmp (details)
  44. [lldb] [Process/gdb-remote] Correct more missing (details)
  45. [X86] Remove unused argument from a helper function. NFC (details)
  46. [X86] Change a SmallVector& argument to SmallVectorImpl&. NFC (details)
  47. [ARM] Fix for buildbots (details)
  48. [X86] Prevent crash in LowerBUILD_VECTORvXi1 for v64i1 vectors on 32-bit (details)
  49. [Unroll] Add an option to control complete unrolling (details)
  50. [TestCommit] Trivial change to test commit access. (details)
  51. [TestCommit] Trivial change to test commit access. (details)
  52. Fix MSVC "result of 32-bit shift implicitly converted to 64 bits" (details)
  53. [llvm-ar] Include a line number when failing to parse an MRI script (details)
Commit dd0170ab24577f76a5c8c78b4f7e068ac29de40c by lebedev.ri
[SimplifyCFG] mergeConditionalStoreToAddress(): consider cost, not
instruction count
Summary: As it can be see in the changed test, while `div` is really
costly, we were speculating it. This does not seem correct.
Also, the old code would run for every single insturuction in BB,
instead of eagerly bailing out as soon as there are too many
instructions.
This function still has a problem that `PHINodeFoldingThreshold` is
per-basic-block, while it should be for all the basic blocks.
Reviewers: efriedma, craig.topper, dmgreen, jmolloy
Reviewed By: jmolloy
Subscribers: xbolva00, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67315
llvm-svn: 372255
The file was modifiedllvm/test/Transforms/SimplifyCFG/X86/merge-cond-stores-cost.ll
The file was modifiedllvm/lib/Transforms/Utils/SimplifyCFG.cpp
Commit 366ab0d086a457b085e3c9ba1c987d5499079cd6 by Lang Hames
[AArch64] Don't implicitly enable global isel on Darwin if
code-model==large.
Summary: AArch64 GlobalISel doesn't support MachO's large code model, so
this patch adds a check for that combination before implicitly enabling
it.
Reviewers: paquette
Subscribers: kristof.beyls, ributzka, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67724
llvm-svn: 372256
The file was addedllvm/test/CodeGen/AArch64/arm64-code-model-large-darwin.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64TargetMachine.cpp
Commit b646dd92c2385d31104057e8ff6f651b28c931b6 by lebedev.ri
[InstCombine] foldUnsignedUnderflowCheck(): handle last few cases
(PR43251)
Summary: I don't have a direct motivational case for this, but it would
be good to have this for completeness/symmetry.
This pattern is basically the motivational pattern from
https://bugs.llvm.org/show_bug.cgi?id=43251 but with different predicate
that requires that the offset is non-zero.
The completeness bit comes from the fact that a similar pattern (offset
!= zero) will be needed for https://bugs.llvm.org/show_bug.cgi?id=43259,
so it'd seem to be good to not overlook very similar patterns..
Proofs: https://rise4fun.com/Alive/21b
Also, there is something odd with `isKnownNonZero()`, if the non-zero
knowledge was specified as an assumption, it didn't pick it up (PR43267)
With this, i see no other missing folds for
https://bugs.llvm.org/show_bug.cgi?id=43251
Reviewers: spatel, nikic, xbolva00
Reviewed By: spatel
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67412
llvm-svn: 372257
The file was modifiedllvm/test/Transforms/InstCombine/result-of-usub-is-non-zero-and-no-overflow.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
Commit a042aa1d829bbf37dc1feeca66d1c3fe77d53272 by lebedev.ri
[CodeGen][X86][NFC] Tests for (sub Carry, X) -> (addcarry (sub 0, X), 0,
Carry) fold (D62392)
llvm-svn: 372258
The file was modifiedllvm/test/CodeGen/X86/subcarry.ll
Commit c00f3182243d097382b71af199719c3027d96900 by lebedev.ri
[DAGCombine][ARM][X86] (sub Carry, X)  ->  (addcarry (sub 0, X), 0,
Carry)  fold
Summary:
`DAGCombiner::visitADDLikeCommutative()` already has a sibling fold:
`(add X, Carry) -> (addcarry X, 0, Carry)`
This fold, as suggested by @efriedma, helps recover from //some// of the
regressions of D62266
Reviewers: efriedma, deadalnix
Subscribers: javed.absar, kristof.beyls, llvm-commits, efriedma
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62392
llvm-svn: 372259
The file was modifiedllvm/test/CodeGen/ARM/addsubcarry-promotion.ll
The file was modifiedllvm/test/CodeGen/X86/subcarry.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Commit f88e75525d253a2af2e5ccfc860673aedbafc552 by dimitry
On PowerPC, Secure-PLT by default for FreeBSD 13 and higher
Summary: In https://svnweb.freebsd.org/changeset/base/349351, FreeBSD 13
and higher transitioned to Secure-PLT for PowerPC.  This part contains
the changes in llvm's PPC subtarget.
Reviewers: emaste, jhibbits, hfinkel
Reviewed By: jhibbits
Subscribers: wuzish, nemanjai, krytarowski, kbarton, MaskRay, jsji,
shchenz, steven.zhang, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67118
llvm-svn: 372260
The file was modifiedllvm/lib/Target/PowerPC/PPCSubtarget.cpp
Commit ab8b456ce5d85d3143b04475449733b2f5e02233 by dimitry
On PowerPC, Secure-PLT by default for FreeBSD 13 and higher
Summary: In https://svnweb.freebsd.org/changeset/base/349351, FreeBSD 13
and higher transitioned to Secure-PLT for PowerPC.  This part contains
the changes in clang's PPC architecture defaults.
Reviewers: emaste, jhibbits, hfinkel
Reviewed By: jhibbits
Subscribers: wuzish, nemanjai, krytarowski, kbarton, MaskRay, jsji,
shchenz, steven.zhang, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D67119
llvm-svn: 372261
The file was modifiedclang/lib/Driver/ToolChains/Arch/PPC.cpp
Commit feea722cf3dc9bcabec7350cfb3e8ac9ed19de10 by lebedev.ri
[SimplifyCFG] mergeConditionalStoreToAddress(): try to pacify MSAN
MSAN bot complains that there is use-of-uninitialized-value of this
FreeStores later in IsWorthwhile(). Perhaps FreeStores needs to be
stored in a vector?
llvm-svn: 372262
The file was modifiedllvm/lib/Transforms/Utils/SimplifyCFG.cpp
Commit 3425a896767621d2cb594edbca16424c3ee8b73d by l.lunak
fix build, adjust test also for Windows path separator
Introduced in 1e9c1d2b7bfc.
llvm-svn: 372263
The file was modifiedclang/test/Frontend/rewrite-includes-conditions.c
The file was modifiedclang/test/Frontend/rewrite-includes.c
Commit 070598bb529a9ac1b10e4c65a9644c90855255c4 by dblaikie
llvm-reduce: Add pass to reduce basic blocks
Patch by Diego Treviño!
Differential Revision: https://reviews.llvm.org/D66320
llvm-svn: 372264
The file was addedllvm/tools/llvm-reduce/deltas/ReduceBasicBlocks.h
The file was addedllvm/test/Reduce/Inputs/remove-bbs.py
The file was modifiedllvm/tools/llvm-reduce/CMakeLists.txt
The file was modifiedllvm/tools/llvm-reduce/DeltaManager.h
The file was addedllvm/tools/llvm-reduce/deltas/ReduceBasicBlocks.cpp
The file was addedllvm/test/Reduce/remove-bbs.ll
Commit 79718839d282506f1c2d5e439fc433e94c3abf3f by llvmgnsyncbot
gn build: Merge r372264
llvm-svn: 372265
The file was modifiedllvm/utils/gn/secondary/llvm/tools/llvm-reduce/BUILD.gn
Commit e40ef12bfad0108024d7d3979565096843bb29a7 by sbc
[lld][WebAssembly] Fix use after free of archive path
This was fixed in the ELF backend in https://reviews.llvm.org/D34554.
Differential Revision: https://reviews.llvm.org/D67676
llvm-svn: 372266
The file was modifiedlld/wasm/InputFiles.h
Commit 68eae4985995f06a8bbfadb9cf420a66cbfbe04a by akhuang
Add AutoUpgrade function to add new address space datalayout string to
existing datalayouts.
Summary: Add function to AutoUpgrade to change the datalayout of old X86
datalayout strings. This adds "-p270:32:32-p271:32:32-p272:64:64" to X86
datalayouts that are otherwise valid and don't already contain it.
This also removes the compatibility changes in
https://reviews.llvm.org/D66843. Datalayout change in
https://reviews.llvm.org/D64931.
Reviewers: rnk, echristo
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67631
llvm-svn: 372267
The file was modifiedllvm/lib/Bitcode/Reader/BitcodeReader.cpp
The file was modifiedllvm/lib/Target/X86/X86TargetMachine.h
The file was modifiedllvm/include/llvm/IR/AutoUpgrade.h
The file was addedllvm/test/Bitcode/upgrade-datalayout.ll
The file was modifiedllvm/lib/Target/X86/X86TargetMachine.cpp
The file was modifiedllvm/include/llvm/Target/TargetMachine.h
The file was modifiedllvm/unittests/Bitcode/CMakeLists.txt
The file was addedllvm/test/Bitcode/upgrade-datalayout3.ll
The file was modifiedllvm/lib/IR/AutoUpgrade.cpp
The file was addedllvm/unittests/Bitcode/DataLayoutUpgradeTest.cpp
The file was addedllvm/test/Bitcode/upgrade-datalayout2.ll
Commit bdad30a8b8fa48a62a37e7400b3ae5a99a6aca53 by llvmgnsyncbot
gn build: Merge r372267
llvm-svn: 372268
The file was modifiedllvm/utils/gn/secondary/llvm/unittests/Bitcode/BUILD.gn
Commit b8ac93c73b618dd9bec20dc2d94ec9afb0140780 by kristof.umann
[analyzer] PR43102: Fix an assertion and an out-of-bounds error for
diagnostic location construction
Summary: https://bugs.llvm.org/show_bug.cgi?id=43102
In today's edition of "Is this any better now that it isn't crashing?",
I'd like to show you a very interesting test case with loop widening.
Looking at the included test case, it's immediately obvious that this is
not only a false positive, but also a very bad bug report in general. We
can see how the analyzer mistakenly invalidated `b`, instead of its
pointee, resulting in it reporting a null pointer dereference error. Not
only that, the point at which this change of value is noted at is at the
loop, rather then at the method call.
It turns out that `FindLastStoreVisitor` works correctly, rather the
supplied explodedgraph is faulty, because `BlockEdge` really is the
`ProgramPoint` where this happens.
{F9855739} So it's fair to say that this needs improving on multiple
fronts. In any case, at least the crash is gone.
Full ExplodedGraph: {F9855743}
Reviewers: NoQ, xazax.hun, baloghadamsoftware, Charusso, dcoughlin,
rnkovacs, TWeaver
Subscribers: JesperAntonsson, uabelho, Ka-Ka, bjope, whisperity, szepet,
a.sidorin, mikhail.ramalho, donat.nagy, dkrupp, gamesh411, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D66716
llvm-svn: 372269
The file was modifiedclang/lib/Analysis/PathDiagnostic.cpp
The file was modifiedclang/lib/StaticAnalyzer/Core/BugReporterVisitors.cpp
The file was addedclang/test/Analysis/loop-widening.cpp
Commit c4da7eeccde607dc7a0d9efe0ddf299aee54ef01 by dblaikie
llvm-reduce: Fix inconsistencies between int/unsigned usage (standardize
on int)
llvm-svn: 372270
The file was modifiedllvm/tools/llvm-reduce/deltas/Delta.cpp
The file was modifiedllvm/tools/llvm-reduce/deltas/Delta.h
The file was modifiedllvm/tools/llvm-reduce/deltas/ReduceArguments.cpp
The file was modifiedllvm/tools/llvm-reduce/deltas/ReduceFunctions.cpp
The file was modifiedllvm/tools/llvm-reduce/deltas/ReduceGlobalVars.cpp
The file was modifiedllvm/tools/llvm-reduce/deltas/ReduceMetadata.cpp
The file was modifiedllvm/tools/llvm-reduce/deltas/ReduceBasicBlocks.cpp
Commit 69a92352022338417f27bfa45c0471beb6a92cc7 by dblaikie
llvm-reduce: Remove inaccurate doxy comment about a return that isn't
returned
Addressing post-commit code review feedback from Dávid Bolvanský -
thanks!
llvm-svn: 372271
The file was modifiedllvm/tools/llvm-reduce/deltas/ReduceBasicBlocks.cpp
Commit 0779dffbd4a927d7bf9523482481248c51796907 by Adrian Prantl
Remove the obsolete BlockByRefStruct flag from LLVM IR
DIFlagBlockByRefStruct is an unused DIFlag that originally was used by
clang to express (Objective-)C block captures in debug info. For the
last year Clang has been emitting complex DIExpressions to describe
block captures instead, which makes all the code supporting this flag
redundant.
This patch removes the flag and all supporting "dead" code, so we can
reuse the bit for something else in the future.
Since this only affects debug info generated by Clang with the block
extension this mostly affects Apple platforms and I don't have any
bitcode compatibility concerns for removing this. The Verifier will
reject debug info that uses the bit and thus degrade gracefully when
LTO'ing older bitcode with a newer compiler.
rdar://problem/44304813
Differential Revision: https://reviews.llvm.org/D67453
llvm-svn: 372272
The file was modifiedllvm/include/llvm/IR/DebugInfoMetadata.h
The file was modifiedllvm/test/CodeGen/ARM/debug-info-blocks.ll
The file was modifiedllvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
The file was modifiedllvm/bindings/go/llvm/dibuilder.go
The file was modifiedllvm/test/DebugInfo/Generic/block-asan.ll
The file was modifiedllvm/include/llvm-c/DebugInfo.h
The file was modifiedllvm/lib/CodeGen/AsmPrinter/DwarfUnit.h
The file was modifiedllvm/include/llvm/IR/DebugInfoFlags.def
The file was modifiedllvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
The file was modifiedllvm/lib/CodeGen/AsmPrinter/DwarfDebug.h
The file was modifiedllvm/lib/IR/Verifier.cpp
The file was modifiedllvm/test/Verifier/blockbyref.ll
Commit ce65ebc39e5bac42308038aab90507611d319d26 by Jessica Paquette
[AArch64][GlobalISel] Support lowering musttail calls
Since we now lower most tail calls, it makes sense to support musttail.
Instead of always falling back to SelectionDAG, only fall back when a
musttail call was not able to be emitted as a tail call. Once we can
handle most incoming and outgoing arguments, we can change this to a
`report_fatal_error` like in ISelLowering.
Remove the assert that we don't have varargs and a musttail, and replace
it with a return false. Implementing this requires that we implement
`saveVarArgRegisters` from AArch64ISelLowering, which is an entirely
different patch.
Add GlobalISel lines to vararg-tallcall.ll to make sure that we produce
correct code. Right now we only fall back, but eventually this will be
relevant.
Differential Revision: https://reviews.llvm.org/D67681
llvm-svn: 372273
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64CallLowering.cpp
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/call-translator-musttail.ll
The file was modifiedllvm/test/CodeGen/AArch64/vararg-tallcall.ll
Commit 8535ba6fa01e355521398c164e5b3d665be2125b by d4m1887
[Docs] Moves topics to new categories
This commit moves several topics to new categories. It also removes a
few duplicate links in Subsystem Documentation.
llvm-svn: 372274
The file was modifiedllvm/docs/ProgrammingDocumentation.rst
The file was modifiedllvm/docs/SubsystemDocumentation.rst
The file was modifiedllvm/docs/index.rst
The file was modifiedllvm/docs/UserGuides.rst
Commit dbcd7f560270890ee0857b86721bf561103192d8 by tlively
[WebAssembly] Restore defaults for stores per memop
Summary: Large slowdowns were observed in Rust due to many small,
constant sized copies in conjunction with poorly-optimized memory.copy
implementations. Since memory.copy cannot be expected to be inlined
efficiently by engines at this time, stop using it for the smallest
copies. We continue to lower all memcpy intrinsics to memory.copy,
though.
Reviewers: aheejin, alexcrichton
Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, JDevlieghere,
sunfish, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67639
llvm-svn: 372275
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
The file was modifiedllvm/test/CodeGen/WebAssembly/bulk-memory.ll
Commit 73778e9878fab279b4f8654d3eecff2571c6398b by rtereshin
[utils] Amend update_llc_test_checks.py to non-llc tooling, NFC
Very minor change aiming to make it easier to extend the script
downstream to support non-llc, but llc-like tools. The main objective is
to decrease the probability of merge conflicts.
llvm-svn: 372276
The file was modifiedllvm/utils/update_llc_test_checks.py
Commit 84c368e2e22f240565f76fbd396af7544b30b60d by rtereshin
[utils] Add minimal support for MIR inputs to update_llc_test_checks.py
update_{llc,mir}_test_checks.py applicability is determined by the
output (assembly or MIR), not the input, which makes
update_llc_test_checks.py the right tool to generate tests that start at
MIR and stop at the final assembly.
This commit adds the minimal support for this path. Main limitation that
remains:
- MIR has to have LLVM IR section, and the CHECK lines will be inserted
into the LLVM IR functions that correspond to the MIR functions.
Running
../utils/update_llc_test_checks.py --llc-binary ./bin/llc on a slightly
modified  ../test/CodeGen/X86/bad-tls-fold.mir
produces the following diff:
+# NOTE: Assertions have been autogenerated by
utils/update_llc_test_checks.py
+# RUN: llc %s -o - | FileCheck %s
--- |
  target triple = "x86_64-unknown-linux-gnu"
@@ -6,17 +7,31 @@
  @i = external thread_local global i32
   define i32 @or() {
+  ; CHECK-LABEL: or:
+  ; CHECK:       # %bb.0: # %entry
+  ; CHECK-NEXT:    movq {{.*}}(%rip), %rax
+  ; CHECK-NEXT:    orq $7, %rax
+  ; CHECK-NEXT:    movq i@{{.*}}(%rip), %rcx
+  ; CHECK-NEXT:    orq %rax, %rcx
+  ; CHECK-NEXT:    movl %fs:(%rcx), %eax
+  ; CHECK-NEXT:    retq
  entry:
    ret i32 undef
  }
-
  define i32 @and() {
+  ; CHECK-LABEL: and:
+  ; CHECK:       # %bb.0: # %entry
+  ; CHECK-NEXT:    movq {{.*}}(%rip), %rax
+  ; CHECK-NEXT:    orq $7, %rax
+  ; CHECK-NEXT:    movq i@{{.*}}(%rip), %rcx
+  ; CHECK-NEXT:    andq %rax, %rcx
+  ; CHECK-NEXT:    movl %fs:(%rcx), %eax
+  ; CHECK-NEXT:    retq
  entry:
    ret i32 undef
  }
...
(not applied)
llvm-svn: 372277
The file was modifiedllvm/utils/update_llc_test_checks.py
Commit 4fd11c1e456ef36ce7c49c51c9daef6d0ffd8cbc by shal1t712
[Object] Extend MachOUniversalBinary::getObjectForArch
Make the method MachOUniversalBinary::getObjectForArch return
MachOUniversalBinary::ObjectForArch and add helper methods
MachOUniversalBinary::getMachOObjectForArch,
MachOUniversalBinary::getArchiveForArch for those who explicitly expect
to get a MachOObjectFile or an Archive.
Differential revision: https://reviews.llvm.org/D67700
Test plan: make check-all
llvm-svn: 372278
The file was modifiedllvm/include/llvm/Object/MachOUniversal.h
The file was modifiedllvm/lib/DebugInfo/Symbolize/Symbolize.cpp
The file was modifiedllvm/lib/Object/Object.cpp
The file was modifiedllvm/tools/llvm-lipo/llvm-lipo.cpp
The file was modifiedllvm/lib/Object/MachOUniversal.cpp
The file was modifiedllvm/tools/llvm-objdump/MachODump.cpp
The file was modifiedllvm/lib/ProfileData/Coverage/CoverageMappingReader.cpp
Commit fa7f168a371200456b1dd237302597260c22f99e by dblaikie
llvm-reduce: Avoid use-after-free when removing a branch instruction
Found my msan buildbot & pointed out by Nico Weber - thanks Nico!
llvm-svn: 372280
The file was modifiedllvm/tools/llvm-reduce/deltas/ReduceBasicBlocks.cpp
Commit e93aded7f02d661234ad81aac0785ccdef6a79dd by sguelton
Initialize all fields in ABIArgInfo.
Due to usage of an uninitialized fields, we end up with a Conditional
jump or move depends on uninitialised value
Fixes https://bugs.llvm.org/show_bug.cgi?id=40547
Commited on behalf of Martin Liska <mliska@suse.cz>
llvm-svn: 372281
The file was modifiedclang/include/clang/CodeGen/CGFunctionInfo.h
Commit 798fe477e39db137ec0f76c94cbee17761bdef0a by dblaikie
llvm-reduce: Add pass to reduce instructions
Patch by Diego Treviño!
Differential Revision: https://reviews.llvm.org/D66263
llvm-svn: 372282
The file was modifiedllvm/test/Reduce/Inputs/remove-global-vars.py
The file was addedllvm/tools/llvm-reduce/deltas/ReduceInstructions.cpp
The file was modifiedllvm/tools/llvm-reduce/CMakeLists.txt
The file was addedllvm/test/Reduce/Inputs/remove-instructions.py
The file was modifiedllvm/test/Reduce/Inputs/remove-bbs.py
The file was modifiedllvm/test/Reduce/remove-global-vars.ll
The file was addedllvm/test/Reduce/remove-instructions.ll
The file was modifiedllvm/tools/llvm-reduce/DeltaManager.h
The file was addedllvm/tools/llvm-reduce/deltas/ReduceInstructions.h
Commit 98a57332ef0e4b859e74a3a43f7f31e9ff1683e0 by llvmgnsyncbot
gn build: Merge r372282
llvm-svn: 372283
The file was modifiedllvm/utils/gn/secondary/llvm/tools/llvm-reduce/BUILD.gn
Commit 21143b93a6ee1121b96ee7f4a75ee542580ba57c by tlively
[WebAssembly] Sort output data sections to place .bss last
Summary: This was always the intended behavior, but had not been
implemented. This ordering is important for Emscripten when generating
.mem files while compiling to JS, since only zeros at the end of
initialized memory can be dropped.
Fixes https://github.com/emscripten-core/emscripten/issues/8999
Reviewers: sbc100
Subscribers: dschuff, jgravelle-google, aheejin, sunfish, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67736
llvm-svn: 372284
The file was addedlld/test/wasm/custom-section-name.ll
The file was modifiedlld/test/wasm/relocatable.ll
The file was modifiedlld/test/wasm/data-layout.ll
The file was modifiedlld/test/wasm/tls-align.ll
The file was modifiedlld/test/wasm/data-segments.ll
The file was modifiedlld/wasm/OutputSegment.h
The file was modifiedlld/test/wasm/reloc-addend.ll
The file was modifiedlld/test/wasm/data-segment-merging.ll
The file was modifiedlld/test/wasm/tls.ll
The file was modifiedlld/wasm/Writer.cpp
Commit d8399d12cd851dacd8f3e1be8b7ca79372626f38 by Matthew.Arsenault
GlobalISel: Don't materialize immarg arguments to intrinsics
Encode them directly as an imm argument to G_INTRINSIC*.
Since now intrinsics can now define what parameters are required to be
immediates, avoid using registers for them. Intrinsics could potentially
want a constant that isn't a legal register type. Also, since G_CONSTANT
is subject to CSE and legalization, transforms could potentially obscure
the value (and create extra work for the selector). The register bank of
a G_CONSTANT is also meaningful, so this could throw off future folding
and legalization logic for AMDGPU.
This will be much more convenient to work with than needing to call
getConstantVRegVal and checking if it may have failed for every constant
intrinsic parameter. AMDGPU has quite a lot of intrinsics wth immarg
operands, many of which need inspection during lowering. Having to find
the value in a register is going to add a lot of boilerplate and waste
compile time.
SelectionDAG has always provided TargetConstant for constants which
should not be legalized or materialized in a register. The distinction
between Constant and TargetConstant was somewhat fuzzy, and there was no
automatic way to force usage of TargetConstant for certain intrinsic
parameters. They were both ultimately ConstantSDNode, and it was
inconsistently used. It was quite easy to mis-select an instruction
requiring an immediate. For SelectionDAG, start emitting TargetConstant
for these arguments, and using timm to match them.
Most of the work here is to cleanup target handling of constants. Some
targets process intrinsics through intermediate custom nodes, which need
to preserve TargetConstant usage to match the intrinsic expectation.
Pattern inputs now need to distinguish whether a constant is merely
compatible with an operand or whether it is mandatory.
The GlobalISelEmitter needs to treat timm as a special case of a leaf
node, simlar to MachineBasicBlock operands. This should also enable
handling of patterns for some G_* instructions with immediates, like
G_FENCE or G_EXTRACT.
This does include a workaround for a crash in GlobalISelEmitter when ARM
tries to uses "imm" in an output with a "timm" pattern source.
llvm-svn: 372285
The file was modifiedllvm/lib/Target/SystemZ/SystemZOperators.td
The file was modifiedllvm/include/llvm/Target/TargetSelectionDAG.td
The file was modifiedllvm/lib/Target/X86/X86InstrSystem.td
The file was modifiedllvm/lib/Target/SystemZ/SystemZInstrVector.td
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_vs.ll
The file was modifiedllvm/lib/Target/X86/X86InstrTSX.td
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/InstructionSelector.h
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgcn-sendmsg.ll
The file was modifiedllvm/lib/Target/SystemZ/SystemZOperands.td
The file was modifiedllvm/lib/Target/X86/X86InstrSSE.td
The file was modifiedllvm/lib/Target/Mips/MipsSEISelLowering.cpp
The file was modifiedllvm/lib/Target/Mips/MipsMSAInstrInfo.td
The file was modifiedllvm/lib/Target/AMDGPU/VOP1Instructions.td
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
The file was modifiedllvm/lib/Target/ARM/ARMInstrThumb2.td
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
The file was modifiedllvm/lib/Target/SystemZ/SystemZISelLowering.cpp
The file was modifiedllvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
The file was modifiedllvm/lib/Target/Mips/Mips64InstrInfo.td
The file was modifiedllvm/lib/Target/Mips/MipsDSPInstrInfo.td
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-struct-return-intrinsics.ll
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrVSX.td
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
The file was modifiedllvm/lib/Target/X86/X86ISelDAGToDAG.cpp
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
The file was modifiedllvm/lib/Target/ARM/ARMInstrInfo.td
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoA.td
The file was modifiedllvm/lib/Target/SystemZ/SystemZSelectionDAGInfo.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrAltivec.td
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.td
The file was modifiedllvm/lib/Target/Hexagon/HexagonDepMapAsm2Intrin.td
The file was modifiedllvm/lib/Target/AMDGPU/SIInstructions.td
The file was modifiedllvm/lib/Target/SystemZ/SystemZPatterns.td
The file was modifiedllvm/utils/TableGen/GlobalISelEmitter.cpp
The file was modifiedllvm/lib/Target/Mips/MicroMipsDSPInstrInfo.td
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrFormats.td
The file was modifiedllvm/lib/Target/Hexagon/HexagonIntrinsics.td
The file was modifiedllvm/lib/Target/AMDGPU/BUFInstructions.td
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.sleep.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_ps.ll
The file was modifiedllvm/lib/Target/X86/X86InstrAVX512.td
The file was modifiedllvm/lib/Target/AMDGPU/SOPInstructions.td
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.exp.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.s.sendmsg.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
The file was modifiedllvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp.mir
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyInstrBulkMemory.td
The file was modifiedllvm/lib/Target/X86/X86InstrMMX.td
The file was modifiedllvm/lib/Target/X86/X86InstrXOP.td
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/lib/Target/Mips/MipsInstrInfo.td
The file was modifiedllvm/lib/Target/AMDGPU/DSInstructions.td
The file was modifiedllvm/lib/Target/SystemZ/SystemZInstrFormats.td
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
The file was modifiedllvm/lib/Target/AMDGPU/VOP3Instructions.td
The file was addedllvm/test/TableGen/immarg.td
The file was modifiedllvm/lib/Target/Hexagon/HexagonDepOperands.td
Commit 22e2c09515e33f11955e7af6dfd09de093c5385b by Matthew.Arsenault
AMDGPU/GlobalISel: Fix RegBankSelect G_SMULH/G_UMULH pre-gfx9
The scalar versions were only introduced in gfx9.
llvm-svn: 372286
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umulh.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smulh.mir
Commit c189f023ac44d64e7d245e08dee53003da74f5d1 by Matthew.Arsenault
MachineScheduler: Fix assert from not checking subregs
The assert would fail if there was a dead def of a subregister if there
was a previous use of a different subregister.
llvm-svn: 372287
The file was modifiedllvm/lib/CodeGen/ScheduleDAGInstrs.cpp
The file was addedllvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir
The file was modifiedllvm/include/llvm/CodeGen/ScheduleDAGInstrs.h
Commit 01213407c4114f5b587b29eae11f0a417666f965 by Matthew.Arsenault
Fix typo
llvm-svn: 372288
The file was modifiedllvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir
Commit a30d022db6d4c0b7f16c50c322667eedd45553d2 by Matthew.Arsenault
AMDGPU/GlobalISel: Attempt to RegBankSelect image intrinsics
Images should always have 2 consecutive, mandatory SGPR arguments.
llvm-svn: 372289
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.sample.1d.ll
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.load.1d.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h
Commit a62ef58346818bbd30201dc81a4d10ecfc1c9ca9 by Matthew.Arsenault
AMDGPU/GlobalISel: RegBankSelect llvm.amdgcn.raw.buffer.{load|store}
llvm-svn: 372290
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.buffer.load.ll
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.buffer.store.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
Commit 838ff36553ae4933134ee0a383a238bbedcba0ec by Matthew.Arsenault
AMDGPU/GlobalISel: RegBankSelect struct buffer load/store
llvm-svn: 372291
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.store.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.load.ll
Commit 67f1f6ff8c07b5eef7239679a6b534efe933ceaa by Matthew.Arsenault
AMDGPU/GlobalISel: Select llvm.amdgcn.raw.buffer.store
llvm-svn: 372292
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was removedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.buffer.store.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
Commit 494243597b46350a248ee25efb0e3a728fc5900c by Matthew.Arsenault
AMDGPU/GlobalISel: Select llvm.amdgcn.raw.buffer.store.format
This needs special handling due to some subtargets that have a
nonstandard register layout for f16 vectors
Also reject some illegal types on other targets.
llvm-svn: 372293
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f16.ll
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f32.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
Commit c15aa241f8213334f6980b7981cee1f28f81112a by yhs
[CLANG][BPF] change __builtin_preserve_access_index() signature
The clang intrinsic __builtin_preserve_access_index() currently has
signature:
const void * __builtin_preserve_access_index(const void * ptr)
This may cause compiler warning when:
- parameter type is "volatile void *" or "const volatile void *", or
- the assign-to type of the intrinsic does not have "const" qualifier.
Further, this signature does not allow dereference of the builtin result
pointer as it is a "const void *" type, which adds extra step for the
user to do type casting.
Let us change the signature to:
PointerT __builtin_preserve_access_index(PointerT ptr) such that the
result and argument types are the same. With this, directly
dereferencing the builtin return value becomes possible.
Differential Revision: https://reviews.llvm.org/D67734
llvm-svn: 372294
The file was modifiedclang/test/Sema/builtin-preserve-access-index.c
The file was modifiedclang/lib/Sema/SemaChecking.cpp
The file was modifiedclang/docs/LanguageExtensions.rst
The file was modifiedclang/include/clang/Basic/DiagnosticSemaKinds.td
The file was modifiedclang/include/clang/Basic/Builtins.def
Commit 4f663a63677d71fbeaeab29d716525fd8cfe1477 by Matthew.Arsenault
AMDGPU/GlobalISel: RegBankSelect tbuffer load/store
These have the same operand structure as the non-t buffer operations.
llvm-svn: 372296
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
Commit bffbeecb44a4a727784b1777e56fe8c9a0fea3fb by Matthew.Arsenault
AMDGPU/GlobalISel: RegBankSelect llvm.amdgcn.ds.swizzle
llvm-svn: 372297
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.swizzle.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
Commit 9f4c7571a1fedd627218b62535a378f85e1fe43c by tstellar
AMDGPU/SILoadStoreOptimizer: Add const to more functions
Reviewers: arsenm, pendingchaos, rampitec, nhaehnle, vpykhtin
Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye,
hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D65901
llvm-svn: 372298
The file was modifiedllvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
Commit 84dc688bc71f26257866070f2e33170dfb336065 by maskray
[Builtins] Delete setjmp_syscall and qsetjmp
Similar to the resolution of gcc PR71876. Nobody uses them or needs the
[-Wincomplete-setjmp-declaration] diagnostic.
llvm-svn: 372299
The file was modifiedclang/include/clang/Basic/Builtins.def
Commit c36b0bf31067b258af59b9f865cef5a091bf906f by mgorny
[lldb] [Process/gdb-remote] Correct more missing
LLDB_INVALID_SIGNAL_NUMBER
Correct more uses of 0 instead of LLDB_INVALID_SIGNAL_NUMBER.
Differential Revision: https://reviews.llvm.org/D67727
llvm-svn: 372300
The file was modifiedlldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
Commit eff4fd69998217837ba8b1d7a2e0394d21e34949 by craig.topper
[X86] Remove unused argument from a helper function. NFC
llvm-svn: 372301
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit d103bb654fe1e7adf60b085c295a38b182859a7d by craig.topper
[X86] Change a SmallVector& argument to SmallVectorImpl&. NFC
Avoids repeating the size.
llvm-svn: 372302
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit 56aa691c4149a20c28b1ec3a1f0ee06b591fa49c by sam.parker
[ARM] Fix for buildbots
I had missed that massive.mir also needed updating.
llvm-svn: 372303
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/massive.mir
Commit c2d25ed1b36d1c9cd02421b09635c1ee55b8099d by craig.topper
[X86] Prevent crash in LowerBUILD_VECTORvXi1 for v64i1 vectors on 32-bit
targets when the vector is a mix of constants and non-constant.
We need to materialize the constants as two 32-bit values that are
casted to v32i1 and then concatenated.
llvm-svn: 372304
The file was modifiedllvm/test/CodeGen/X86/avx512-mask-op.ll
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit a44768858c75ae3e020bb2951af00743ae48742e by serguei.katkov
[Unroll] Add an option to control complete unrolling
Add an ability to specify the max full unroll count for LoopUnrollPass
pass in pass options.
Reviewers: fhahn, fedor.sergeev Reviewed By: fedor.sergeev Subscribers:
hiraditya, zzheng, dmgreen, llvm-commits Differential Revision:
https://reviews.llvm.org/D67701
llvm-svn: 372305
The file was modifiedllvm/lib/Passes/PassBuilder.cpp
The file was modifiedllvm/lib/Transforms/Scalar/LoopUnrollPass.cpp
The file was modifiedllvm/include/llvm/Transforms/Scalar/LoopUnrollPass.h
The file was modifiedllvm/lib/Transforms/Scalar/LoopUnrollAndJamPass.cpp
The file was addedllvm/test/Transforms/LoopUnroll/disable-full-unroll-by-opt.ll
The file was modifiedllvm/include/llvm/Transforms/Utils/UnrollLoop.h
Commit 5e7c76aa382967b5792f2c448df9eab9fbcd2322 by mark.murray
[TestCommit] Trivial change to test commit access.
llvm-svn: 372306
The file was modifiedclang/bindings/python/README.txt
Commit 8a12e40185cd0ce7031e6abab4af12e6fc923110 by mark.murray
[TestCommit] Trivial change to test commit access.
llvm-svn: 372307
The file was modifiedclang/bindings/python/README.txt
Commit da89495a3e73bfc02ffb7d881da1db628d1d0815 by llvm-dev
Fix MSVC "result of 32-bit shift implicitly converted to 64 bits"
warning. NFCI.
llvm-svn: 372308
The file was modifiedllvm/lib/Target/ARM/ARMBasicBlockInfo.h
Commit 04398c729b20c16aa06bfab4330cf1831d1f8dec by gbreynoo
[llvm-ar] Include a line number when failing to parse an MRI script
Errors that occur when reading an MRI script now include a corresponding
line number.
Differential Revision: https://reviews.llvm.org/D67449
llvm-svn: 372309
The file was addedllvm/test/tools/llvm-ar/mri-errors.test
The file was modifiedllvm/test/tools/llvm-ar/mri-addlib.test
The file was modifiedllvm/tools/llvm-ar/llvm-ar.cpp