Changes

Summary

1. [NVPTX] Add support for ISD::ABS lowering Use the ISD::ABS opcode directly Differential Revision: https://reviews.llvm.org/D32944
2. [X86][SSE] Break register dependencies on v16i8/v8i16 BUILD_VECTOR on SSE41 rL294581 broke unnecessary register dependencies on partial v16i8/v8i16 BUILD_VECTORs, but on SSE41 we (currently) use insertion for full BUILD_VECTORs as well. By allowing full insertion to occur on SSE41 targets we can break register dependencies here as well.

Revision 302356 by rksimon: [NVPTX] Add support for ISD::ABS lowering Use the ISD::ABS opcode directly Differential Revision: https://reviews.llvm.org/D32944
Change Type	Path in Repository	Path in Workspace
	/llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.cpp (diff)	llvm-revision.src/llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.cpp
	/llvm/trunk/lib/Target/NVPTX/NVPTXInstrInfo.td (diff)	llvm-revision.src/llvm/trunk/lib/Target/NVPTX/NVPTXInstrInfo.td
Revision 302355 by rksimon: [X86][SSE] Break register dependencies on v16i8/v8i16 BUILD_VECTOR on SSE41 rL294581 broke unnecessary register dependencies on partial v16i8/v8i16 BUILD_VECTORs, but on SSE41 we (currently) use insertion for full BUILD_VECTORs as well. By allowing full insertion to occur on SSE41 targets we can break register dependencies here as well.
Change Type	Path in Repository	Path in Workspace
	/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (diff)	llvm-revision.src/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
	/llvm/trunk/test/CodeGen/X86/shuffle-vs-trunc-512.ll (diff)	llvm-revision.src/llvm/trunk/test/CodeGen/X86/shuffle-vs-trunc-512.ll
	/llvm/trunk/test/CodeGen/X86/vector-shuffle-variable-128.ll (diff)	llvm-revision.src/llvm/trunk/test/CodeGen/X86/vector-shuffle-variable-128.ll