Started 2 yr 7 mo ago
Took 1 hr 28 min on green-dragon-13

Success Build r302555 (#5806) (May 9, 2017 11:27:25 AM)

Subproject Builds

Revision: 302555
Changes
  1. Revert r302547 ([mips] Impose a threshold for coercion of aggregates)

    Reverting
      Modified MipsABIInfo::classifyArgumentType so that it now coerces
      aggregate structures only if the size of said aggregate is less than 16/64
      bytes, depending on the ABI.
    as it broke clang-with-lto-ubuntu builder. (detail/ViewSVN)
    by petarj
  2. [RegScavenger] Rangify a loop, NFC (detail/ViewSVN)
    by kparzysz
  3. Adding VSCode syntax colorizer to utils (generated from textmate colorizer).
    --This line, and those below, will be igored--

    A    utils/vscode
    A    utils/vscode/README
    A    utils/vscode/tablegen
    A    utils/vscode/tablegen/.vscode
    A    utils/vscode/tablegen/.vscode/launch.json
    A    utils/vscode/tablegen/CHANGELOG.md
    A    utils/vscode/tablegen/README.md
    A    utils/vscode/tablegen/language-configuration.json
    A    utils/vscode/tablegen/package.json
    A    utils/vscode/tablegen/syntaxes
    A    utils/vscode/tablegen/syntaxes/TableGen.tmLanguage
    A    utils/vscode/tablegen/vsc-extension-quickstart.md (detail/ViewSVN)
    by zer0
  4. [NewGVN] Fix a consistent order for phi nodes operands.

    The way we currently define congruency for two PHIExpression(s) is:

    1) The operands to the phi functions are congruent
    2) The PHIs are defined in the same BasicBlock.

    NewGVN works under the assumption that phi operands are in predecessor
    order, or at least in some consistent order. OTOH, is valid IR:

    patatino:
      %meh = phi i16 [ %0, %winky ], [ %conv1, %tinky ]
      %banana = phi i16 [ %0, %tinky ], [ %conv1, %winky ]
      br label %end

    and the in-memory representations of the two SSA registers have an
    inconsistent order. This violation of NewGVN assumptions results into
    two PHIs found congruent when they're not. While we think it's useful
    to have always a consistent order enforced, let's fix this in NewGVN
    sorting uses in predecessor order before creating a PHI expression.

    Differential Revision:  https://reviews.llvm.org/D32990 (detail/ViewSVN)
    by davide
  5. [APInt] Remove return value from tcFullMultiply.

    The description says it returns the number of words needed to represent the results. But the way it was coded it always returns (lhsWords + rhsWords) or (lhsWords + rhsWords - 1). But the result could be even smaller than that and it wouldn't tell you.

    No one uses the result today so rather than try to fix it, just remove it. (detail/ViewSVN)
    by ctopper
  6. NewGVN: Make all of symbolic evaluation logically const. (detail/ViewSVN)
    by dannyb
  7. [X86] Add more patterns for BZHI isel

    This patch adds more patterns that a reasonable person might write that can be compiled to BZHI.

    This adds support for

    (~0U >> (32 - b)) & a;

    and

    a << (32 - b) >> (32 - b);

    This was inspired by the code in APInt::clearUnusedBits.

    This can pass an index of 32 to the bzhi instruction which a quick test of Haswell hardware shows will not mask any bits. Though the description text in the Intel manual says the "index is saturated to OperandSize-1". The pseudocode in the same manual indicates no bits will be zeroed for this case.

    I think this is still missing cases where the subtract portion is an 8-bit operation.

    Differential Revision: https://reviews.llvm.org/D32616 (detail/ViewSVN)
    by ctopper
  8. [InstCombineCasts] Fix checks in sext->lshr->trunc pattern.

    The comment says to avoid the case where zero bits are shifted into the truncated value,
    but the code checks that the shift is smaller than the truncated value instead of the
    number of bits added by the sign extension. Fixing this allows a shift by more than the
    value size to be introduced, which is undefined behavior, so the shift is capped at the
    value size minus one, which has the expected behavior of filling the value with the sign
    bit.

    Patch by Jacob Young!

    Differential Revision: https://reviews.llvm.org/D32285 (detail/ViewSVN)
    by spatel
  9. [mips] Impose a threshold for coercion of aggregates

    Modified MipsABIInfo::classifyArgumentType so that it now coerces aggregate
    structures only if the size of said aggregate is less than 16/64 bytes,
    depending on the ABI.

    Patch by Stefan Maksimovic.

    Differential Revision: https://reviews.llvm.org/D32900 (detail/ViewSVN)
    by petarj
  10. VX512] Only look at lower bit in constant scalar masks

    for scalar masked instructions only the lower bit of the mask is relevant. so for constant masks we should either do an unmasked operation or no operation, depending on the value of the lower bit.
    This patch handles cases where the lower bit is '1'.

    Differential Revision: https://reviews.llvm.org/D32805 (detail/ViewSVN)
    by guyblank
  11. [CodeCompletion] Complete platform names in @available expressions

    rdar://32074504 (detail/ViewSVN)
    by arphaman
  12. Re-land "Use the frame index side table for byval and inalloca arguments"

    This re-lands r302483. It was not the cause of PR32977. (detail/ViewSVN)
    by rnk
  13. Re-land "Don't add DBG_VALUE instructions for static allocas in dbg.declare"

    This re-lands commit r302461. It was not the cause of PR32977. (detail/ViewSVN)
    by rnk
  14. Revert r302476 "Update testcase for upstream LLVM changes."

    That test update was for r302469, which was reverted in r302533 due to PR32977. (detail/ViewSVN)
    by hans
  15. Allow compiler-rt to find lld and libc++ parallel to LLVM, as in the monorepo (detail/ViewSVN)
    by rnk

Started by upstream project phase2_modules_relay build number 3975
originally caused by:

This run spent:

  • 9 ms waiting;
  • 1 hr 28 min build duration;
  • 1 hr 28 min total from scheduled to completion.