Started 1 mo 24 days ago
Took 18 hr on green-dragon-09

Failed Build #5455 (Aug 29, 2019 5:16:40 PM)

Revisions
  • http://llvm.org/svn/llvm-project/llvm/trunk : 370423
  • http://llvm.org/svn/llvm-project/cfe/trunk : 370422
  • http://llvm.org/svn/llvm-project/compiler-rt/trunk : 370390
  • http://llvm.org/svn/llvm-project/debuginfo-tests/trunk : 364589
  • http://llvm.org/svn/llvm-project/libcxx/trunk : 370240
  • http://llvm.org/svn/llvm-project/clang-tools-extra/trunk : 370379
Changes
  1. DebugInfo: add CodeView register mapping for ARM NT

    Add the core registers and NEON registers mapping to the CodeView
    register ID.  This is sufficient to compile a basic C program with debug
    info using CodeView debug info. (detail/ViewSVN)
    by Saleem Abdulrasool
  2. [Modules] Make ReadModuleMapFileBlock errors reliable

    This prevents a crash when an error should be emitted instead.

    During implicit module builds, there are cases where ReadASTCore is called with
    ImportedBy set to nullptr, which breaks expectations in ReadModuleMapFileBlock,
    leading to crashes.

    Fix this by improving ReadModuleMapFileBlock to handle ImportedBy correctly.
    This only happens non deterministically in the wild, when the underlying file
    system changes while concurrent compiler invocations use implicit modules,
    forcing rebuilds which see an inconsistent filesystem state. That said, there's
    no much to do w.r.t. writing tests here.

    rdar://problem/48828801 (detail/ViewSVN)
    by Bruno Lopes
  3. [CMake][Fuchsia] Enable experimental pass manager by default

    We plan on using experimental new pass manager for Fuchsia toolchain.

    Differential Revision: https://reviews.llvm.org/D58214 (detail/ViewSVN)
    by phosek
  4. [clang-scan-deps] reuse the file manager across invocations of
    the dependency scanner on a single worker thread

    This behavior can be controlled using the new `-reuse-filemanager` clang-scan-deps
    option. By default the file manager is reused.

    The added test/ClangScanDeps/symlink.cpp is able to pass with
    the reused filemanager after the related FileEntryRef changes
    landed earlier. The test test/ClangScanDeps/subframework_header_dir_symlink.m
    still fails when the file manager is reused (I run the FileCheck with not to
    make it PASS). I will address this in a follow-up patch that improves
    the DirectoryEntry name modelling in the FileManager. (detail/ViewSVN)
    by arphaman
  5. Fix silent wrong-code bugs and crashes with designated initialization.

    We failed to correctly handle the 'holes' left behind by designated
    initializers in VerifyOnly mode. This would result in us thinking that a
    designated initialization would be valid, only to find that it is not
    actually valid when we come to build it. In a +Asserts build, that would
    assert, and in a -Asserts build, that would silently lose some part of
    the initialization or crash.

    With this change, when an InitListExpr contains any designators, we now
    always build a structured list so that we can track the locations of the
    'holes' that we need to go back and fill in.

    We could in principle do better: we only need the structured form if
    there is a designator that jumps backwards (and can otherwise check for
    the holes as we progress through the initializer list), but dealing with
    that turns out to be rather complicated, so it's not done as part of
    this patch. (detail/ViewSVN)
    by rsmith
  6. Refactor InitListChecker to check only a single (explicit) initializer
    list, rather than recursively checking multiple lists in C.

    This simplification is in preparation for making InitListChecker
    maintain more state that's specific to the explicit initializer list,
    particularly when handling designated initialization. (detail/ViewSVN)
    by rsmith
  7. Refactor InitListChecker to make it a bit clearer that hasError is only
    set to true in VerifyOnly mode in cases where it's also set to true when
    actually building the initializer list.

    Add FIXMEs for the two cases where that's not true. No functionality
    change intended. (detail/ViewSVN)
    by rsmith
  8. [WebAssembly] Make __attribute__((used)) not imply export.

    Add an WASM_SYMBOL_NO_STRIP flag, so that __attribute__((used)) doesn't
    need to imply exporting. When targeting Emscripten, have
    WASM_SYMBOL_NO_STRIP imply exporting.

    Differential Revision: https://reviews.llvm.org/D62542 (detail/ViewSVN)
    by djg
  9. [Tests] Precommit a few cases where we're missing oppurtunities for block local simplications off assumes. (detail/ViewSVN)
    by reames
  10. [NFC] Test commit - sorted headers. (detail/ViewSVN)
    by nand
  11. [PowerPC] Support extended mnemonics mffprwz etc.

    Summary:
    Reported in https://github.com/opencv/opencv/issues/15413.

    We have serveral extended mnemonics for Move To/From Vector-Scalar Register Instructions
    eg: mffprd,mtfprd etc.

    We only support one of them, this patch add the others.

    Reviewers: nemanjai, steven.zhang, hfinkel, #powerpc

    Reviewed By: hfinkel

    Subscribers: wuzish, qcolombet, hiraditya, kbarton, MaskRay, shchenz, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D66963 (detail/ViewSVN)
    by jsji
  12. [AArch64][GlobalISel] Select arithmetic extended register patterns

    This teaches GISel to select patterns which fold an extend plus optional shift
    into the addressing mode. In particular, adds and subs.

    Factor out the arith extended register ComplexPatterns in AArch64InstrFormats.td
    and create GISel equivalents.

    Add some equivalent functions to the ones in AArch64ISelDAGToDAG:

    - `selectArithExtendedRegister`
    - `narrowExtendRegIfNeeded`
    - `getExtendTypeForInst`

    `getExtendTypeForInst` includes the checks for loads and stores. This will be
    used for WRO addressing modes in loads + stores.

    Teach selectCopy to properly handle subregister copies on the same bank in
    order to support `narrowExtendRegIfNeeded`. The extended register must be a
    GPR32, so we need to support same-bank subregister copies.

    Fix a bug in getSubRegForClass which would cause registers on things like
    GPR32common to end up getting ssub. Just change the check to look for FPR32
    rather than GPR32.

    For tests:

    - Add select-arith-extended-reg.mir
    - Update addsub_ext.ll to include GlobalISel checks

    Differential Revision: https://reviews.llvm.org/D66835 (detail/ViewSVN)
    by paquette
  13. [X86] Don't emit unreachable stack adjustments

    Summary:
    This is a minor improvement on our past attempts to do this. Fixes
    PR43155.

    Reviewers: hans

    Subscribers: hiraditya, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D66905 (detail/ViewSVN)
    by rnk
  14. Allow '@' to appear in x86 mingw symbols

    Summary:
    There is no reason to differ in assembler behavior here between -msvc
    and -gnu targets. Without this setting, the text after the '@' is
    interpreted as a symbol variable, like foo@IMGREL.

    Reviewers: mstorsjo

    Subscribers: hiraditya, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D66974 (detail/ViewSVN)
    by rnk
  15. [InstCombine] add possible bswap as widening shuffle test; NFC

    Goes with the proposal in D66965. (detail/ViewSVN)
    by spatel
  16. [CFG] Fix CFG for statement-expressions in return values.

    We're building the CFG from bottom to top, so when the return-value expression
    has a non-trivial CFG on its own, we need to continue building from the entry
    to the return-value expression CFG rather than from the block to which
    we've just appended the return statement.

    Fixes a false positive warning "control may reach end of non-void function". (detail/ViewSVN)
    by dergachev
  17. Fix the build for MSVC builds using M_PI (detail/ViewSVN)
    by rnk
  18. [X86][SSE] combinePMULDQ - pmuldq(x, 0) -> zero vector (PR43159)

    ISD::isBuildVectorAllZeros permits undef elements to be present, which means we can't return it as a zero vector. PMULDQ/PMULUDQ is an extending multiply so a multiply by zero of the lower 32-bits should result in a zero 64-bit element. (detail/ViewSVN)
    by rksimon
  19. [ASan] Version mismatch check follow-up

    Follow-up for:
    [ASan] Make insertion of version mismatch guard configurable
    3ae9b9d5e40d1d9bdea1fd8e6fca322df920754a

    This tiny change makes sure that this test passes on our internal bots
    as well. (detail/ViewSVN)
    by yln
  20. AMDGPU/GlobalISel: Legalize sin/cos (detail/ViewSVN)
    by arsenm
  21. Avoid crash when dumping NULL Type as JSON.

    Patch by Bert Belder. (detail/ViewSVN)
    by aaronballman
  22. Remove `FileManager::invalidateCache` as it has no callers anymore. NFC. (detail/ViewSVN)
    by vsapsai
  23. [InstCombine] reduce duplicated code; NFC (detail/ViewSVN)
    by spatel
  24. Revert [MBP] Disable aggressive loop rotate in plain mode

    This reverts r369664 (git commit 51f48295cbe8fa3a44db263b528dd9f7bae7bf9a)

    It causes many benchmark regressions, internally and in llvm's benchmark suite. (detail/ViewSVN)
    by rupprecht
  25. Revert enabling MemorySSA.

    Breaks sanitizers bots.

    Differential Revision: https://reviews.llvm.org/D58311 (detail/ViewSVN)
    by asbirlea
  26. [X86] Remove what little support we had for MPX

    -Deprecate -mmpx and -mno-mpx command line options
    -Remove CPUID detection of mpx for -march=native
    -Remove MPX from all CPUs
    -Remove MPX preprocessor define

    I've left the "mpx" string in the backend so we don't fail on old IR, but its not connected to anything.

    gcc has also deprecated these command line options. https://www.phoronix.com/scan.php?page=news_item&px=GCC-Patch-To-Drop-MPX

    Differential Revision: https://reviews.llvm.org/D66669 (detail/ViewSVN)
    by ctopper
  27. GlobalISel: Don't compute known bits for non-integral GEP (detail/ViewSVN)
    by arsenm
  28. [LoopUnrollAndJam] Use Lazy strategy for DTU.

    We can also apply the earlier updates to the lazy DTU, instead of
    applying them directly.

    Reviewers: kuhar, brzycki, asbirlea, SjoerdMeijer

    Reviewed By: brzycki, asbirlea, SjoerdMeijer

    Differential Revision: https://reviews.llvm.org/D66918 (detail/ViewSVN)
    by fhahn
  29. [cmake] enable x86 libfuzzer on Windows

        - recent commit https://reviews.llvm.org/D66433 enabled libfuzzer
        to build on windows, this just enables the option to build as part
        of the the regular build. (detail/ViewSVN)
    by mcgov
  30. GlobalISel: Add maskedValueIsZero and signBitIsZero to known bits

    I dropped the DemandedElts since it seems to be missing from some of
    the new interfaces, but not others. (detail/ViewSVN)
    by arsenm
  31. GlobalISel: Add known bits to InstructionSelector

    AMDGPU uses this for some addressing mode selection patterns. The
    analysis run itself doesn't do anything so it seems easier to just
    always require this than adding a way to opt in. (detail/ViewSVN)
    by arsenm
  32. [MemorySSA & LoopPassManager] Enable MemorySSA as loop dependency. Update tests.

    Summary:
    I'm not planning to check this in at the moment, but feedback is very welcome, in particular how this affects performance.
    The feedback obtains here will guide the next steps towards enabling this.

    This patch enables the use of MemorySSA in the loop pass manager.

    Passes that currently use MemorySSA:
    - EarlyCSE
    Passes that use MemorySSA after this patch:
    - EarlyCSE
    - LICM
    - SimpleLoopUnswitch
    Loop passes that update MemorySSA (and do not use it yet, but could use it after this patch):
    - LoopInstSimplify
    - LoopSimplifyCFG
    - LoopUnswitch
    - LoopRotate
    - LoopSimplify
    - LCSSA
    Loop passes that do *not* update MemorySSA:
    - IndVarSimplify
    - LoopDelete
    - LoopIdiom
    - LoopSink
    - LoopUnroll
    - LoopInterchange
    - LoopUnrollAndJam
    - LoopVectorize
    - LoopReroll
    - IRCE

    Reviewers: chandlerc, george.burgess.iv, davide, sanjoy, gberry

    Subscribers: jlebar, Prazek, dmgreen, jdoerfert, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D58311 (detail/ViewSVN)
    by asbirlea
  33. Added 'inline' to functions defined in headers to avoid ODR violations (detail/ViewSVN)
    by gribozavr
  34. [GlobalISel][AArch64] Select llvm.aarch64.stxr* intrinsics.

    Add a GISelPredicateCode to the stxr_* PatFrags in AArch64InstrAtomics.td.

    This allows us to select these intrinsics.

    Differential Revision: https://reviews.llvm.org/D65779 (detail/ViewSVN)
    by paquette
  35. [InstCombine] add tests for bswap disguised as shuffle; NFC

    Somewhat motivating case In PR43146:
    https://bugs.llvm.org/show_bug.cgi?id=43146

    But that's a lot more complicated. (detail/ViewSVN)
    by spatel
  36. [GlobalISel][AArch64] Use a GISelPredicateCode to select llvm.aarch64.stlxr.*

    Remove manual selection code for this intrinsic and use a GISelPredicateCode
    instead.

    This allows us to fully select this intrinsic without any tricky custom C++
    matching.

    Differential Revision: https://reviews.llvm.org/D65780 (detail/ViewSVN)
    by paquette
  37. Changed FrontendActionFactory::create to return a std::unique_ptr

    Subscribers: jkorous, arphaman, kadircet, cfe-commits

    Tags: #clang

    Differential Revision: https://reviews.llvm.org/D66947 (detail/ViewSVN)
    by gribozavr
  38. [AArch64][GlobalISel] Select @llvm.aarch64.ldxr.* intrinsics

    Same thing as D66897, but for ldxr.* instead. Add a GISelPredicateCode to the
    ldxr_* definitions, which allows us to import them.

    Add select-ldxr-intrin.mir, and update arm64-ldxr-stxr.ll.

    Differential Revision: https://reviews.llvm.org/D66898 (detail/ViewSVN)
    by paquette
  39. [AArch64][GlobalISel] Select @llvm.aarch64.ldaxr.* intrinsics

    Add a GISelPredicateCode to ldaxr_*. This allows us to import the patterns for
    @llvm.aarch64.ldaxr.*, and thus select them.

    Add `isLoadStoreOfNumBytes` for the GISelPredicateCode, since each of these
    intrinsics involves the same check.

    Add select-ldaxr-intrin.mir, and update arm64-ldxr-stxr.ll.

    Differential Revision: https://reviews.llvm.org/D66897 (detail/ViewSVN)
    by paquette
  40. [SimplifyCFG] Skip sinking common lifetime markers of `alloca`.

    Summary:
    - Similar to the workaround in fix of PR30188, skip sinking common
      lifetime markers of `alloca`. They are mostly left there after
      inlining functions in branches.

    Subscribers: hiraditya, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D66950 (detail/ViewSVN)
    by hliao
  41. [PowerPC][NFC] Update fp-int-conversions-direct-moves.ll using script

    Also add -ppc-asm-full-reg-names,-ppc-vsr-nums-as-vr. (detail/ViewSVN)
    by jsji
  42. [Clangd] NFC: Added fixme for checking for local/anonymous types for extracted parameters (detail/ViewSVN)
    by sureyeaah
  43. [clangd] Update out-of-date links in readme, NFC. (detail/ViewSVN)
    by hokein
  44. [NFC][SimplifyCFG] 'Safely extract low bits' pattern will also benefit from -phi-node-folding-threshold=3

    This is the naive implementation of x86 BZHI/BEXTR instruction:
    it takes input and bit count, and extracts low nbits up to bit width.
    I.e. unlike shift it does not have any UB when nbits >= bitwidth.
    Which means we don't need a while PHI here, simple select will do.
    And if it's a select, it should then be trivial to fix codegen
    to select it to BEXTR/BZHI.

    See https://bugs.llvm.org/show_bug.cgi?id=34704 (detail/ViewSVN)
    by lebedevri
  45. [clangd][NFC] Update background-index command line description

    Summary:
    We didn't change this in D64019 just in case we revert it back.
    Deleting it now.

    Reviewers: hokein, sammccall

    Subscribers: ilya-biryukov, MaskRay, jkorous, arphaman, cfe-commits

    Tags: #clang

    Differential Revision: https://reviews.llvm.org/D66943 (detail/ViewSVN)
    by kadircet
  46. [DAGCombine] Fix shadow variable warnings. NFCI. (detail/ViewSVN)
    by rksimon
  47. DWARFDebugLoc: Make parsing and error reporting more robust

    Summary:
    While examining this class for possible use in lldb, I noticed two
    things:
    - it spits out parsing errors directly to stderr
    - the loclists parser can incorrectly return valid location lists when
      parsing malformed (truncated) data

    I improve the stderr situation by making the parseOneLocationList
    functions return Expected<T>s. The errors are still dumped to stderr by
    their callers, so this is only a partial fix, but it is enough for my
    use case, as I intend to parse the locations lists one by one.

    I fix the behavior in the truncated scenario by using the newly
    introduced DataExtractor Cursor API.

    I also add tests for handling the error cases, as they currently have no
    coverage.

    Reviewers: dblaikie, JDevlieghere, probinson

    Subscribers: lldb-commits, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D63591 (detail/ViewSVN)
    by labath
  48. Removed a function declaration that doesn't have a definition (detail/ViewSVN)
    by gribozavr
  49. [RISCV] Fix callee-saved-gprs.ll test ABIs (detail/ViewSVN)
    by luismarques
  50. Allow replaceAndRecursivelySimplify to list unsimplified visitees.

    This is part of D65280 and split it to avoid ABI changes on the 9.0
    release branch. (detail/ViewSVN)
    by joerg
  51. [mips] Inline emitStoreWithSymOffset and emitLoadWithSymOffset methods. NFC

    Both methods `MipsTargetStreamer::emitStoreWithSymOffset` and
    `MipsTargetStreamer::emitLoadWithSymOffset` are almost the same and
    differ argument names only. These methods are used in the single place
    so it's better to inline their code and remove original methods. (detail/ViewSVN)
    by atanasyan
  52. [mips] Fix expanding `lw/sw $reg1, symbol($reg2)` instruction

    When a "base" in the `lw/sw $reg1, symbol($reg2)` instruction is
    a register and generated code is position independent, backend
    does not add the "base" value to the symbol address.
    ```
    lw     $reg1, %got(symbol)($gp)
    lw/sw  $reg1, 0($reg1)
    ```

    This patch fixes the bug and adds the missed `addu` instruction by
    passing `BaseReg` into the `loadAndAddSymbolAddress` routine and handles
    the case when the `BaseReg` is the zero register to escape redundant
    `move reg, reg` instruction:
    ```
    lw     $reg1, %got(symbol)($gp)
    addu   $reg1, $reg1, $reg2
    lw/sw  $reg1, 0($reg1)
    ```

    Differential Revision: https://reviews.llvm.org/D66894 (detail/ViewSVN)
    by atanasyan
  53. [InstSimplify] Drop leftover "division-by-zero guard" around `@llvm.umul.with.overflow` inverted overflow bit

    Summary:
    Now that with D65143/D65144 we've produce `@llvm.umul.with.overflow`,
    and with D65147 we've flattened the CFG, we now can see that
    the guard may have been there to prevent division by zero is redundant.
    We can simply drop it:
    ```
    ----------------------------------------
    Name: no overflow or zero
      %iszero = icmp eq i4 %y, 0
      %umul = smul_overflow i4 %x, %y
      %umul.ov = extractvalue {i4, i1} %umul, 1
      %umul.ov.not = xor %umul.ov, -1
      %retval.0 = or i1 %iszero, %umul.ov.not
      ret i1 %retval.0
    =>
      %iszero = icmp eq i4 %y, 0
      %umul = smul_overflow i4 %x, %y
      %umul.ov = extractvalue {i4, i1} %umul, 1
      %umul.ov.not = xor %umul.ov, -1
      %retval.0 = or i1 %iszero, %umul.ov.not
      ret i1 %umul.ov.not

    Done: 1
    Optimization is correct!
    ```
    Note that this is inverted from what we have in a previous patch,
    here we are looking for the inverted overflow bit.
    And that inversion is kinda problematic - given this particular
    pattern we neither hoist that `not` closer to `ret` (then the pattern
    would have been identical to the one without inversion,
    and would have been handled by the previous patch), neither
    do the opposite transform. But regardless, we should handle this too.
    I've filled [[ https://bugs.llvm.org/show_bug.cgi?id=42720 | PR42720 ]].

    Reviewers: nikic, spatel, xbolva00, RKSimon

    Reviewed By: spatel

    Subscribers: hiraditya, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D65151 (detail/ViewSVN)
    by lebedevri
  54. [InstSimplify] Drop leftover "division-by-zero guard" around `@llvm.umul.with.overflow` overflow bit

    Summary:
    Now that with D65143/D65144 we've produce `@llvm.umul.with.overflow`,
    and with D65147 we've flattened the CFG, we now can see that
    the guard may have been there to prevent division by zero is redundant.
    We can simply drop it:
    ```
    ----------------------------------------
    Name: no overflow and not zero
      %iszero = icmp ne i4 %y, 0
      %umul = umul_overflow i4 %x, %y
      %umul.ov = extractvalue {i4, i1} %umul, 1
      %retval.0 = and i1 %iszero, %umul.ov
      ret i1 %retval.0
    =>
      %iszero = icmp ne i4 %y, 0
      %umul = umul_overflow i4 %x, %y
      %umul.ov = extractvalue {i4, i1} %umul, 1
      %retval.0 = and i1 %iszero, %umul.ov
      ret %umul.ov

    Done: 1
    Optimization is correct!
    ```

    Reviewers: nikic, spatel, xbolva00

    Reviewed By: spatel

    Subscribers: hiraditya, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D65150 (detail/ViewSVN)
    by lebedevri
  55. [SimplifyCFG] FoldTwoEntryPHINode(): don't bailout on i1 PHI's if we can hoist a 'not' from incoming values

    Summary:
    As it can be seen in the tests in D65143/D65144, even though we have formed an '@llvm.umul.with.overflow'
    and got rid of potential for division-by-zero, the control flow remains, we still have that branch.

    We have this condition:
    ```
      // Don't fold i1 branches on PHIs which contain binary operators
      // These can often be turned into switches and other things.
      if (PN->getType()->isIntegerTy(1) &&
          (isa<BinaryOperator>(PN->getIncomingValue(0)) ||
           isa<BinaryOperator>(PN->getIncomingValue(1)) ||
           isa<BinaryOperator>(IfCond)))
        return false;
    ```
    which was added back in rL121764 to help with `select` formation i think?

    That check prevents us to flatten the CFG here, even though we know
    we no longer need that guard and will be able to drop everything
    but the '@llvm.umul.with.overflow' + `not`.

    As it can be seen from tests, we end here because the `not` is being
    sinked into the PHI's incoming values by InstCombine,
    so we can't workaround this by hoisting it to after PHI.

    Thus i suggest that we relax that check to not bailout if we'd get to hoist the `not`.

    Reviewers: craig.topper, spatel, fhahn, nikic

    Reviewed By: spatel

    Subscribers: hiraditya, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D65147 (detail/ViewSVN)
    by lebedevri
  56. [InstCombine] Fold '((%x * %y) u/ %x) != %y' to '@llvm.umul.with.overflow' + overflow bit extraction

    Summary:
    `((%x * %y) u/ %x) != %y` is one of (3?) common ways to check that
    some unsigned multiplication (will not) overflow.
    Currently, we don't catch it. We could:
    ```
    $ /repositories/alive2/build-Clang-unknown/alive -root-only ~/llvm-patch1.ll
    Processing /home/lebedevri/llvm-patch1.ll..

    ----------------------------------------
    Name: no overflow
      %o0 = mul i4 %y, %x
      %o1 = udiv i4 %o0, %x
      %r = icmp ne i4 %o1, %y
      ret i1 %r
    =>
      %n0 = umul_overflow i4 %x, %y
      %o0 = extractvalue {i4, i1} %n0, 0
      %o1 = udiv %o0, %x
      %r = extractvalue {i4, i1} %n0, 1
      ret %r

    Done: 1
    Optimization is correct!

    ----------------------------------------
    Name: no overflow
      %o0 = mul i4 %y, %x
      %o1 = udiv i4 %o0, %x
      %r = icmp eq i4 %o1, %y
      ret i1 %r
    =>
      %n0 = umul_overflow i4 %x, %y
      %o0 = extractvalue {i4, i1} %n0, 0
      %o1 = udiv %o0, %x
      %n1 = extractvalue {i4, i1} %n0, 1
      %r = xor %n1, -1
      ret i1 %r

    Done: 1
    Optimization is correct!

    ```

    Reviewers: nikic, spatel, efriedma, xbolva00, RKSimon

    Reviewed By: nikic

    Subscribers: hiraditya, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D65144 (detail/ViewSVN)
    by lebedevri
  57. [InstCombine] Fold '(-1 u/ %x) u< %y' to '@llvm.umul.with.overflow' + overflow bit extraction

    Summary:
    `(-1 u/ %x) u< %y` is one of (3?) common ways to check that
    some unsigned multiplication (will not) overflow.
    Currently, we don't catch it. We could:
    ```
    ----------------------------------------
    Name: no overflow
      %o0 = udiv i4 -1, %x
      %r = icmp ult i4 %o0, %y
    =>
      %o0 = udiv i4 -1, %x
      %n0 = umul_overflow i4 %x, %y
      %r = extractvalue {i4, i1} %n0, 1

    Done: 1
    Optimization is correct!

    ----------------------------------------
    Name: no overflow, swapped
      %o0 = udiv i4 -1, %x
      %r = icmp ugt i4 %y, %o0
    =>
      %o0 = udiv i4 -1, %x
      %n0 = umul_overflow i4 %x, %y
      %r = extractvalue {i4, i1} %n0, 1

    Done: 1
    Optimization is correct!

    ----------------------------------------
    Name: overflow
      %o0 = udiv i4 -1, %x
      %r = icmp uge i4 %o0, %y
    =>
      %o0 = udiv i4 -1, %x
      %n0 = umul_overflow i4 %x, %y
      %n1 = extractvalue {i4, i1} %n0, 1
      %r = xor %n1, -1

    Done: 1
    Optimization is correct!

    ----------------------------------------
    Name: overflow
      %o0 = udiv i4 -1, %x
      %r = icmp ule i4 %y, %o0
    =>
      %o0 = udiv i4 -1, %x
      %n0 = umul_overflow i4 %x, %y
      %n1 = extractvalue {i4, i1} %n0, 1
      %r = xor %n1, -1

    Done: 1
    Optimization is correct!
    ```

    As it can be observed from tests, while simply forming the `@llvm.umul.with.overflow`
    is easy, if we were looking for the inverted answer, then more work needs to be done
    to cleanup the now-pointless control-flow that was guarding against division-by-zero.
    This is being addressed in follow-up patches.

    Reviewers: nikic, spatel, efriedma, xbolva00, RKSimon

    Reviewed By: nikic, xbolva00

    Subscribers: hiraditya, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D65143 (detail/ViewSVN)
    by lebedevri
  58. Fix variable ‘IsInitCapturePack’ set but not used warning. NFCI. (detail/ViewSVN)
    by rksimon
  59. Fix MSVC "not all control paths return a value" warning. NFCI. (detail/ViewSVN)
    by rksimon
  60. Removed `AnyFunctionDecl`, it is unused. (detail/ViewSVN)
    by gribozavr
  61. Removed two function declarations that don't have definitions (detail/ViewSVN)
    by gribozavr
  62. [CostModel] Model all `extractvalue`s as free.

    Summary:
    As disscussed in https://reviews.llvm.org/D65148#1606412,
    `extractvalue` don't actually generate any code,
    so we should treat them as free.

    Reviewers: craig.topper, RKSimon, jnspaulsson, greened, asb, t.p.northover, jmolloy, dmgreen

    Reviewed By: jmolloy

    Subscribers: javed.absar, hiraditya, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D66098 (detail/ViewSVN)
    by lebedevri
  63. [Index] Added a ShouldSkipFunctionBody callback to libIndex, and refactored clients to use it instead of inventing their own solution

    Subscribers: jkorous, arphaman, kadircet, cfe-commits

    Tags: #clang

    Differential Revision: https://reviews.llvm.org/D66879 (detail/ViewSVN)
    by gribozavr
  64. [Index] Stopped wrapping FrontendActions in libIndex and its users

    Exposed a new function, createIndexingASTConsumer, that creates an
    ASTConsumer. ASTConsumers compose well.

    Removed wrapping functionality from createIndexingAction. (detail/ViewSVN)
    by gribozavr
  65. [Index] Moved the IndexDataConsumer::finish call into the IndexASTConsumer from IndexAction

    Doing so removes the last reason to expose a FrontendAction from
    libIndex. (detail/ViewSVN)
    by gribozavr
  66. [CodeGen]: don't treat structures returned in registers as memory inputs

    Summary:
    The "=r" output constraint for a structure variable passed to inline asm
    shouldn't be converted to "=*r", as this changes the asm directive
    semantics and prevents DSE optimizations.
    Instead, preserve the constraints and return such structures as integers
    of corresponding size, which are converted back to structures when
    storing the result.

    Fixes PR42672.

    Subscribers: cfe-commits

    Tags: #clang

    Differential Revision: https://reviews.llvm.org/D65234 (detail/ViewSVN)
    by glider
  67. [DebugInfo] LiveDebugValues: correctly discriminate kinds of variable locations

    The missing line added by this patch ensures that only spilt variable
    locations are candidates for being restored from the stack. Otherwise,
    register or constant-value information can be interpreted as a spill
    location, through a union.

    The added regression test replicates a scenario where this occurs: the
    stack load from [rsp] causes the register-location DBG_VALUE to be
    "restored" to rsi, when it should be left alone. See PR43058 for details.

    Un x-fail a test that was suffering from this from a previous patch.

    Differential Revision: https://reviews.llvm.org/D66895 (detail/ViewSVN)
    by jmorse
  68. Fix signed/unsigned comparison warning. NFCI. (detail/ViewSVN)
    by rksimon
  69. Fix shadow variable warning. NFCI. (detail/ViewSVN)
    by rksimon
  70. [yaml2obj] - Allow placing local symbols after globals.

    This allows us to produce broken binaries with local
    symbols placed after global in '.dynsym'/'.symtab'

    Also, simplifies the code.

    Differential revision: https://reviews.llvm.org/D66799 (detail/ViewSVN)
    by grimar
  71. [llvm-readobj/llvm-readelf] - Report a proper warning when dumping a broken dynamic relocation.

    When we have a dynamic relocation with a broken symbol's st_name,
    tools report a useless error: "Invalid data was encountered while parsing the file".

    After this change we report a warning + "<corrupt>" as a symbol name.

    Differential revision: https://reviews.llvm.org/D66734 (detail/ViewSVN)
    by grimar
  72. [ARM] MVE Masked loads and stores

    Masked loads and store fit naturally with MVE, the instructions being easily
    predicated. This adds lowering for the simple cases of masked loads and stores.
    It does not yet deal with widening/narrowing or pre/post inc.

    The llvm masked load intrinsic will accept a "passthru" value, dictating the
    values used for the zero masked lanes. In MVE the instructions write 0 to the
    zero predicated lanes, so we need to match a passthru that isn't 0 (or undef)
    with a select instruction to pull in the correct data after the load.

    We also need to do something with unaligned loads/stores. Currently this uses a
    similar method used in big endian, using an VLDRB.8 (and potentially a VREV in
    BE). This does mean that the predicate mask is converted from, for example, a
    v4i1 to a v16i1. The VLDR instructions are defined as using the first bit of
    the relevant mask lane, so this could potentially load different results if the
    predicate is little odd. As the input is a v4i1 however, I believe this is OK
    and all the bits required should be set in the predicate, making the VLDRB.8
    load the same data.

    Differential Revision: https://reviews.llvm.org/D66534 (detail/ViewSVN)
    by dmgreen
  73. [DebugInfo] LiveDebugValues should always revisit backedges if it skips them

    The "join" method in LiveDebugValues does not attempt to join unseen
    predecessor blocks if their out-locations aren't yet initialized, instead
    the block should be re-visited later to see if any locations have changed
    validity. However, because the set of blocks were all being "process"'d
    once before "join" saw them, that logic in "join" was actually ignoring
    legitimate out-locations on the first pass through. This meant that some
    invalidated locations were not removed from the head of loops, allowing
    illegal locations to persist.

    Fix this by removing the run of "process" before the main join/process loop
    in ExtendRanges. Now the unseen predecessors that "join" skips truly are
    uninitialized, and we come back to the block at a later time to re-run
    "join", see the @baz function added.

    This also fixes another fault where stack/register transfers in the entry
    block (or any other before-any-loop-block) had their tranfers initially
    ignored, and were then never revisited. The MIR test added tests for this
    behaviour.

    XFail a test that exposes another bug; a fix for this is coming in D66895.

    Differential Revision: https://reviews.llvm.org/D66663 (detail/ViewSVN)
    by jmorse
  74. [X86][CodeGen][NFC] Delay `combineIncDecVector()` from DAGCombine to X86DAGToDAGISel

    Summary:
    We were previously doing it in DAGCombine.
    But we also want to do `sub %x, C` -> `add %x, (sub 0, C)` for vectors in DAGCombine.
    So if we had `sub %x, -1`, we'll transform it to `add %x, 1`,
    which `combineIncDecVector()` will immediately transform back into `sub %x, -1`,
    and here we go again...

    I've marked this as NFC since not a single test changes,
    but since that 'changes' DAGCombine, probably this isn't fully NFC.

    Reviewers: RKSimon, craig.topper, spatel

    Reviewed By: craig.topper

    Subscribers: hiraditya, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D62327 (detail/ViewSVN)
    by lebedevri
  75. [DAGCombiner] (insert_vector_elt (vector_shuffle X, Y), (extract_vector_elt X, N), IdxC) -> (vector_shuffle X, Y)

    Summary: This is beneficial when the shuffle is only used once and end up being generated in a few places when some node is combined into a shuffle.

    Reviewers: craig.topper, efriedma, RKSimon, lebedev.ri

    Subscribers: llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D66718 (detail/ViewSVN)
    by deadalnix
  76. [ARM] Masked load and store and predicate tests. NFC (detail/ViewSVN)
    by dmgreen
  77. [InstCombine] Shift amount reassociation in bittest: trunc-of-lshr (PR42399)

    Summary:
    Finally, the fold i was looking forward to :)

    The legality check is muddy, i doubt  i've groked the full generalization,
    but it handles all the cases i care about, and can come up with:
    https://rise4fun.com/Alive/26j

    I.e. we can perform the fold if **any** of the following is true:
    * The shift amount is either zero or one less than widest bitwidth
    * Either of the values being shifted has at most lowest bit set
    * The value that is being shifted by `shl` (which is not truncated) should have no less leading zeros than the total shift amount;
    * The value that is being shifted by `lshr` (which **is** truncated) should have no less leading zeros than the widest bit width minus total shift amount minus one

    I strongly suspect there is some better generalization, but i'm not aware of it as of right now.
    For now i also avoided using actual `computeKnownBits()`, but restricted it to constants.

    Reviewers: spatel, nikic, xbolva00

    Reviewed By: spatel

    Subscribers: hiraditya, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D66383 (detail/ViewSVN)
    by lebedevri
  78. [Index] Create PP callbacks in the ASTConsumer

    Doing so removes one reason to create a custom FrontendAction.
    FrontendActions are not desirable because they are difficult to compose.
    ASTConsumers are much easier to compose. (detail/ViewSVN)
    by gribozavr
  79. [OpenCL] Fix diagnosing enqueue_kernel call with too few args

    The err_typecheck_call_too_few_args diagnostic takes arguments, but
    none were provided causing clang to crash when attempting to diagnose
    an enqueue_kernel call with too few arguments.

    Fixes llvm.org/PR42045

    Differential Revision: https://reviews.llvm.org/D66883 (detail/ViewSVN)
    by svenvh
  80. [Index] Marked a bunch of classes 'final'

    This file defines multiple inheritance hierarchies and 'final' helps
    with readability. (detail/ViewSVN)
    by gribozavr
  81. LegalizeSetCCCondCode - Reduce scope of NeedSwap to fix cppcheck warning. NFCI.

    No need for this to be defined outside the only switch case its used in. (detail/ViewSVN)
    by rksimon
  82. Fix variable set but no used warnings on NDEBUG builds. NFCI. (detail/ViewSVN)
    by rksimon
  83. Fix variable set but no used warning on NDEBUG builds. NFCI. (detail/ViewSVN)
    by rksimon
  84. [Analyzer] Iterator Checkers - Make range errors and invalidated access fatal

    Range errors (dereferencing or incrementing the past-the-end iterator or
    decrementing the iterator of the first element of the range) and access of
    invalidated iterators lead to undefined behavior. There is no point to
    continue the analysis after such an error on the same execution path, but
    terminate it by a sink node (fatal error). This also improves the
    performance and helps avoiding double reports (e.g. in case of nested
    iterators).

    Differential Revision: https://reviews.llvm.org/D62893 (detail/ViewSVN)
    by baloghadamsoftware
  85. [COFF] Add a ResourceSectionRef method for getting the data entry, print it in llvm-readobj

    Differential Revision: https://reviews.llvm.org/D66819 (detail/ViewSVN)
    by mstorsjo
  86. [COFF] Add a bounds checking helper for iterating a coff_resource_dir_table

    Instead of blindly incrementing pointers in llvm-readobj, use this
    helper, which does bounds checking against the available section
    data.

    Differential Revision: https://reviews.llvm.org/D66818 (detail/ViewSVN)
    by mstorsjo
  87. [COFF] Fix error handling in ResourceSectionRef

    Previously, the expression (Reader.readFoo()) was expanded twice,
    triggering asserts as one of the Error types ends up not checked
    (and as it was expanded twice, the method would end up called twice
    if it failed first).

    Differential Revision: https://reviews.llvm.org/D66817 (detail/ViewSVN)
    by mstorsjo
  88. [llvm-readobj] Print the resource type textually for .res files

    This already is done when dumping resources from coff objects.

    Differential Revision: https://reviews.llvm.org/D66816 (detail/ViewSVN)
    by mstorsjo
  89. [llvm-readobj] Remove a leftover string trim operation. NFC.

    This became unnecessary in SVN r359153.

    Differential Revision: https://reviews.llvm.org/D66815 (detail/ViewSVN)
    by mstorsjo
  90. [clangd] Update themeRuleMatcher when color theme changes in vscode extension.

    Summary:
    Add event listener that listens to configuration changes and reloads the ThemeRuleMatcher when the theme changes.

    Right now it will not recolor the files, depends on the colorizer CL for that.

    Reviewers: hokein, ilya-biryukov

    Subscribers: MaskRay, jkorous, arphaman, kadircet, cfe-commits

    Tags: #clang

    Differential Revision: https://reviews.llvm.org/D66406 (detail/ViewSVN)
    by jvikstrom
  91. Reland "[clangd] Migrate last tweak tests to TweakTesting.h and remove old helpers. NFC"

    This reverts commit 3dcf55aa45bad800533b36b70a14ebeb2b84e219, and avoids
    use of multiline raw strings in macro calls. (detail/ViewSVN)
    by sammccall
  92. [Test][Time profiler] Fix test for python3

    Summary:
    Fix test checking time profiler generates correct tracing json-file.
    `filter` works differently for python2 and python3, so unifying this.

    Reviewers: mgehre, nathanchance

    Subscribers: cfe-commits

    Tags: #clang

    Differential Revision: https://reviews.llvm.org/D66873 (detail/ViewSVN)
    by anton-afanasyev
  93. [X86] Remove isel patterns with X86VBroadcast+scalar_to_vector+load.

    The DAG should have these as X86VBroadcast+load. (detail/ViewSVN)
    by ctopper
  94. Removed dead code from clang/AST/NSAPI.h

    Subscribers: cfe-commits

    Tags: #clang

    Differential Revision: https://reviews.llvm.org/D66884 (detail/ViewSVN)
    by gribozavr
  95. [x86] Adding support for some missing intrinsics: _mm512_cvtsi512_si32

    Summary:
    Adding support for some missing intrinsics:
    _mm512_cvtsi512_si32

    Reviewers: craig.topper, pengfei, LuoYuanke, spatel, RKSimon

    Reviewed By: craig.topper

    Subscribers: llvm-commits

    Patch by Bing Yu (yubing)

    Differential Revision: https://reviews.llvm.org/D66785 (detail/ViewSVN)
    by pengfei
  96. [X86] Remove some unneeded X86VBroadcast isel patterns that have larger than 128 bit input types.

    We should always be shrinking the input to 128 bits or smaller
    when the node is created. (detail/ViewSVN)
    by ctopper

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