Started 2 mo 20 days ago
Took 17 hr on green-dragon-08

Failed Build #5461 (Sep 3, 2019 6:41:22 AM)

  • : 370753
  • : 370744
  • : 370756
  • : 364589
  • : 370599
  • : 370758
  1. [clangd] Fix a data race in test code

    Found by TSan, thanks bkramer for pointing this out. (detail/ViewSVN)
    by ibiryukov
  2. [clangd] Wrong attribute on debug function in r370746 (detail/ViewSVN)
    by sammccall
  3. compiler-rt: use 64-bit time_t for all FreeBSD archs except i386

    At present only i386 has 32-bit time_t on FreeBSD.

    Reviewed by: dim
    Differential Revision: (detail/ViewSVN)
    by emaste
  4. compiler-rt: use more __sanitizer_time_t on FreeBSD

    A few structs were using long for time_t members.  NFC.

    Reviewed by: devnexen
    Differential Revision: (detail/ViewSVN)
    by emaste
  5. [SystemZ]  Recognize INLINEASM_BR in backend.

    SystemZInstrInfo::analyzeBranch() needs to check for INLINEASM_BR
    instructions, or it will crash.

    Review: Ulrich Weigand (detail/ViewSVN)
    by jonpa
  6. gn build: (manually) merge r370499 (detail/ViewSVN)
    by nico
  7. Fix MSVC "not all control paths return a value" warning. NFCI. (detail/ViewSVN)
    by rksimon
  8. gn build: Merge r370746 (detail/ViewSVN)
    by nico
  9. [clangd] Add targetDecl(), which determines what declaration an AST node refers to.

    This is the first part of an effort to "unbundle" our libIndex use into separate
    concerns (AST traversal, token<->node mapping, node<->decl mapping,
    decl<->decl relationshipes).

    Currently, clangd relies on libIndex to associate tokens, AST nodes, and decls.
    This leads to rather convoluted implementations of e.g. hover and
    extract-function, which are not naturally thought of as indexing applications.

    The idea is that by decoupling different concerns, we make them easier
    to use, test, and combine, and more efficient when only one part is needed.
    There are some synergies between e.g. traversal and finding
    relationships between decls, hopefully the benefits outweight these.

    Reviewers: kadircet, ilya-biryukov

    Subscribers: mgorny, MaskRay, jkorous, arphaman, jfb, cfe-commits

    Tags: #clang

    Differential Revision: (detail/ViewSVN)
    by sammccall
  10. [ARM] Ignore Implicit CPSR regs when lowering from Machine to MC operands

    The code here seems to date back to r134705, when tablegen lowering was first
    being added. I don't believe that we need to include CPSR implicit operands on
    the MCInst. This now works more like other backends (like AArch64), where all
    implicit registers are skipped.

    This allows the AliasInst for CSEL's to match correctly, as can be seen in the
    test changes.

    Differential revision: (detail/ViewSVN)
    by dmgreen
  11. [OpenCL] Drop spurious semicolon in generated file; NFC (detail/ViewSVN)
    by svenvh
  12. [SystemZ]  Add support for fentry.

    SystemZAsmPrinter now properly emits function calls to __fentry__.

    Review: Ulrich Weigand (detail/ViewSVN)
    by jonpa
  13. [ARM] Invert CSEL predicates if the opposite is a simpler constant to materialise

    This moves ConstantMaterializationCost into ARMBaseInstrInfo so that it can
    also be used in ISel Lowering, adding codesize values to the computed costs, to
    be able to compare either approximate instruction counts or codesize costs.

    It also adds a HasLowerConstantMaterializationCost, which compares the
    ConstantMaterializationCost of two values, returning true if the first is
    smaller either in instruction count/codesize, or falling back to the other in
    the case that they are equal.

    This is used in constant CSEL lowering to invert the predicate if the opposite
    is easier to materialise.

    Differential revision: (detail/ViewSVN)
    by dmgreen
  14. Fixit for -Wfinal-dtor-non-final-class (detail/ViewSVN)
    by xbolva00
  15. [ARM] Generate 8.1-m CSINC, CSNEG and CSINV instructions.

    Arm 8.1-M adds a number of related CSEL instructions, including CSINC, CSNEG and CSINV. These choose between two values given the content in CPSR and a condition, performing an increment, negation or inverse of the false value.

    This adds some selection for them, either from constant values or patterns. It does not include CSEL directly, which is currently not always making code better. It is still useful, but we will have to check more carefully where it should and shouldn't be used.

    Code by Ranjeet Singh and Simon Tatham, with some modifications from me.

    Differential revision: (detail/ViewSVN)
    by dmgreen
  16. [ARM] Add csel tests. NFC (detail/ViewSVN)
    by dmgreen
  17. Added fixit notes for -Wfinal-dtor-non-final-class (detail/ViewSVN)
    by xbolva00
  18. [mips] Switch to the `.text` section after emitting asm file preamble

    Now the last `.section` directive in the MIPS asm file preamble
    is the `.section .mdebug.abi`. If assembler code injected for example
    by the LLVM `module asm` or the C ` __asm` directives do not contain
    explicit switching to the `.text` section it goes to the `.mdebug.abi`
    section. It might be unexpected to the user and in fact for example
    breaks building some existing code like FreeBSD libc [1].

    The patch forces switching to the `.text` section after emitting MIPS
    assembler file preamble.


    Fix PR43119.

    Differential Revision: (detail/ViewSVN)
    by atanasyan
  19. [ARM] Fix MVE ldst offset ranges

    We were using isShiftedInt<7, Shift>(RHSC) to detect the ranges of offsets to
    fold into MVE loads/stores. The instructions actually take a 7 bit unsigned
    integer which is either added or subtracted. So something more like
    isShiftedUInt<7, Shift>(abs(RHSC)).

    Instead I've changes this to use the isScaledConstantInRange method, same as in
    SelectT2AddrModeImm7Offset used by pre/post inc, which seemed to already be
    getting this correct.

    Differential revision: (detail/ViewSVN)
    by dmgreen
  20. [ARM][MVE] Decoding of VMSR doesn't diagnose some unpredictable encodings

    Decoding of VMSR doesn't diagnose some unpredictable encodings, as the unpredictable bits are not correctly set.

    Diff-reduce this instruction's internals WRT VMRS so I can see the differences better. Mostly this is s/src/Rt/g.

    Fill in the "should-be-(0)" bits.

    Designate the Unpredictable{} bits for both VMRS and VMSR.

    Patch by Mark Murray!

    Differential revision: (detail/ViewSVN)
    by ostannard
  21. Bug fix on function epilog optimization (ARM backend)

    To save a 'add sp,#val' instruction by adding registers to the final pop instruction,
    the first register transferred by this pop instruction need to be found.
    If the function to be optimized has a non-void return value, the operand list contains
    r0 (implicit) which prevents the optimization to take place.
    Therefore implicit register references should be skipped in the search loop,
    because this registers are never popped from the stack.

    Patch by Rainer Herbertz (rOptimizer)!

    Differential revision: (detail/ViewSVN)
    by ostannard
  22. [ARM] More MVE load/store tests for offsets around the negative limit. NFC (detail/ViewSVN)
    by dmgreen
  23. [LV] Fix miscompiles by adding non-header PHI nodes to AllowedExit

    Fold-tail currently supports reduction last-vector-value live-out's,
    but has yet to support last-scalar-value live-outs, including
    non-header phi's. As it relies on AllowedExit in order to detect
    them and bail out we need to add the non-header PHI nodes to
    AllowedExit, otherwise we end up with miscompiles.


    Reviewers: fhahn, Ayal

    Reviewed By: fhahn, Ayal

    Subscribers: anna, hiraditya, rkruppe, llvm-commits

    Tags: #llvm

    Differential Revision: (detail/ViewSVN)
    by bjope
  24. [LV] Precommit test case showing miscompile from PR43166. NFC

    Summary:  Precommit test case showing miscompile from PR43166.

    Reviewers: fhahn, Ayal

    Reviewed By: fhahn

    Subscribers: rkruppe, llvm-commits

    Tags: #llvm

    Differential Revision: (detail/ViewSVN)
    by bjope
  25. [ARM NEON] Avoid duplicated decarations

    The declaration of arm neon intrinsics that are
    "big endian safe" print the same code for big
    and small endian targets.
    This patch avoids duplicates by checking if an
    intrinsic is safe to have a single definition.
    (decreases header 11k lines out of 73k).

    Reviewers: t.p.northover, ostannard, labrinea

    Reviewed By: ostannard

    Subscribers: kristof.beyls, cfe-commits, olista01

    Tags: #clang

    Differential Revision: (detail/ViewSVN)
    by dnsampaio
  26. [LV] Tail-folding, runtime scev checks

    Now that we allow tail-folding, not only when we optimise for size, make
    sure we do not run in this assert.

    Differential revision: (detail/ViewSVN)
    by sjoerdmeijer
  27. [RISCV] Correct Logic around ilp32e macros

    GCC seperates the `__riscv_float_abi_*` macros and the
    `__riscv_abi_rve` macro. If the chosen abi is ilp32e, `gcc -march=rv32i
    -mabi=ilp32i -E -dM` shows that both `__riscv_float_abi_soft` and
    `__riscv_abi_rve` are set.

    This patch corrects the compiler logic around these defines.

    At the moment, this patch will not change clang's behaviour, because we do not
    accept the `ilp32e` abi yet.

    Reviewers: luismarques, asb

    Reviewed By: luismarques

    Subscribers: rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, pzheng, cfe-commits

    Tags: #clang

    Differential Revision: (detail/ViewSVN)
    by lenary
  28. [LV] Tail-folding with runtime memory checks

    The loop vectorizer was running in an assert when it tried to fold the tail and
    had to emit runtime memory disambiguation checks.

    Differential revision: (detail/ViewSVN)
    by sjoerdmeijer
  29. [MachinePipeliner] Add a way to unit-test the schedule emitter

    Emitting a schedule is really hard. There are lots of corner cases to take care of; in fact, of the 60+ SWP-specific testcases in the Hexagon backend most of those are testing codegen rather than the schedule creation itself.

    One issue is that to test an emission corner case we must craft an input such that the generated schedule uses that corner case; sometimes this is very hard and convolutes testcases. Other times it is impossible but we want to test it anyway.

    This patch adds a simple test pass that will consume a module containing a loop and generate pipelined code from it. We use post-instr-symbols as a way to annotate instructions with the stage and cycle that we want to schedule them at.

    We also provide a flag that causes the MachinePipeliner to generate these annotations instead of actually emitting code; this allows us to generate an input testcase with:

      llc < %s -stop-after=pipeliner -pipeliner-annotate-for-testing -o test.mir

    And run the emission in isolation with:

      llc < test.mir -run-pass=modulo-schedule-test (detail/ViewSVN)
    by jamesm
  30. [ARM] Select vmla

    This patch adds vmla selection.

    Differential revision: (detail/ViewSVN)
    by samtebbs
  31. [X86] Simplify the setOperationAction handling for fp_to_uint by improving the Custom handler a bit.

    This merges the 32-bit and 64-bit mode code to just use Custom
    for both i32 and i64. We already had most of the handling in
    the custom handling due to the AVX512 having legal fp_to_uint.
    Just needed to add the i32->i64 promotion handling. Refactor
    the fp_to_uint code in the custom handler to simplify the
    number of times we check things.

    Tweak cost model tables to match the default handling we were
    getting due to Expand before. (detail/ViewSVN)
    by ctopper
  32. [X86] Don't use Expand for i32 fp_to_uint on SSE1/2 targets on 32-bit target.

    Use Custom lowering instead. Fall back to default expansion only
    when the scalar FP type belongs in an XMM register. This improves
    lowering for i32 to fp80, and also i32 to double on SSE1 only. (detail/ViewSVN)
    by ctopper
  33. [X86] Add an exhaustive test for i32 fptosi/fptoui across different triples and features. (detail/ViewSVN)
    by ctopper
  34. [LegalizeDAG] Pass DAG to two calls to SDNode::dump in debug prints so that they will print target specific nodes correctly.

    The dump methods can only print target node names correctly if
    they can get access to the TLI object. (detail/ViewSVN)
    by ctopper
  35. [X86] Custom promote i32->f80 uint_to_fp on AVX512 64-bit targets.

    Reuse the same code to promote all i32 uint_to_fp on 64-bit targets
    to simplify the X86ISelLowering constructor. (detail/ViewSVN)
    by ctopper
  36. [x86] Fix bugs of some intrinsic functions in CLANG : _mm512_stream_ps, _mm512_stream_pd, _mm512_stream_si512

    Reviewers: craig.topper, pengfei, LuoYuanke, RKSimon, spatel

    Reviewed By: RKSimon

    Subscribers: llvm-commits

    Patch by Bing Yu (yubing)

    Differential Revision: (detail/ViewSVN)
    by pengfei
  37. Rename -Wc++20-designator to -Wc++2a-designator for consistency and add
    some test coverage for the flag. (detail/ViewSVN)
    by rsmith
  38. Split -Wreorder into different warnings for reordering a constructor
    mem-initializer list and for reordering a designated initializer list. (detail/ViewSVN)
    by rsmith
  39. [CostModel][X86] Add scalar sext/zext cost tests (detail/ViewSVN)
    by rksimon
  40. [X86] Enable fp128 as a legal type with SSE1 rather than with MMX.

    FP128 values are passed in xmm registers so should be asssociated
    with an SSE feature rather than MMX which uses a different set
    of registers.

    llc enables sse1 and sse2 by default with x86_64. But does not
    enable mmx. Clang enables all 3 features by default.

    I've tried to add command lines to test with -sse
    where possible, but any test that returns a value in an xmm
    register fails with a fatal error with -sse since we have no
    defined ABI for that scenario. (detail/ViewSVN)
    by ctopper

Started by upstream project Clang Stage 2: cmake, R -g Tsan, using Stage 1 RA build number 18244
originally caused by:

Started by upstream project Clang Stage 2: cmake, R -g Tsan, using Stage 1 RA build number 18245
originally caused by:

Started by upstream project Clang Stage 2: cmake, R -g Tsan, using Stage 1 RA build number 18246
originally caused by:

Started by upstream project Clang Stage 2: cmake, R -g Tsan, using Stage 1 RA build number 18247
originally caused by:

Started by upstream project Clang Stage 2: cmake, R -g Tsan, using Stage 1 RA build number 18248
originally caused by:

Started by upstream project Clang Stage 2: cmake, R -g Tsan, using Stage 1 RA build number 18249
originally caused by:

Started by upstream project Clang Stage 2: cmake, R -g Tsan, using Stage 1 RA build number 18250
originally caused by:

Started by upstream project Clang Stage 2: cmake, R -g Tsan, using Stage 1 RA build number 18251
originally caused by:

Started by upstream project Clang Stage 2: cmake, R -g Tsan, using Stage 1 RA build number 18252
originally caused by:

Started by upstream project Clang Stage 2: cmake, R -g Tsan, using Stage 1 RA build number 18253
originally caused by:

Started by upstream project Clang Stage 2: cmake, R -g Tsan, using Stage 1 RA build number 18254
originally caused by:

This run spent:

  • 17 hr waiting;
  • 17 hr build duration;
  • 1 day 11 hr total from scheduled to completion.

Identified problems

Regression test failed

This build failed because a regression test in the test suite FAILed. See the test report for details.
Indication 1

Ninja target failed

Below is a link to the first failed ninja target.
Indication 2

Missing test results

The test result file Jenkins is looking for does not exist after the build.
Indication 3

Compile Error

This build failed because of a compile error. Below is a list of all errors in the build log:
Indication 4