FailedChanges

Summary

  1. [clangd] Fix a data race in test code Found by TSan, thanks bkramer for pointing this out.
  2. [clangd] Wrong attribute on debug function in r370746
  3. compiler-rt: use 64-bit time_t for all FreeBSD archs except i386 At present only i386 has 32-bit time_t on FreeBSD. Reviewed by: dim Differential Revision: https://reviews.llvm.org/D66758
  4. compiler-rt: use more __sanitizer_time_t on FreeBSD A few structs were using long for time_t members. NFC. Reviewed by: devnexen Differential Revision: https://reviews.llvm.org/D66756
  5. [SystemZ] Recognize INLINEASM_BR in backend. SystemZInstrInfo::analyzeBranch() needs to check for INLINEASM_BR instructions, or it will crash. Review: Ulrich Weigand
  6. gn build: (manually) merge r370499
  7. Fix MSVC "not all control paths return a value" warning. NFCI.
  8. gn build: Merge r370746
  9. [clangd] Add targetDecl(), which determines what declaration an AST node refers to. Summary: This is the first part of an effort to "unbundle" our libIndex use into separate concerns (AST traversal, token<->node mapping, node<->decl mapping, decl<->decl relationshipes). Currently, clangd relies on libIndex to associate tokens, AST nodes, and decls. This leads to rather convoluted implementations of e.g. hover and extract-function, which are not naturally thought of as indexing applications. The idea is that by decoupling different concerns, we make them easier to use, test, and combine, and more efficient when only one part is needed. There are some synergies between e.g. traversal and finding relationships between decls, hopefully the benefits outweight these. Reviewers: kadircet, ilya-biryukov Subscribers: mgorny, MaskRay, jkorous, arphaman, jfb, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D66751
  10. [ARM] Ignore Implicit CPSR regs when lowering from Machine to MC operands The code here seems to date back to r134705, when tablegen lowering was first being added. I don't believe that we need to include CPSR implicit operands on the MCInst. This now works more like other backends (like AArch64), where all implicit registers are skipped. This allows the AliasInst for CSEL's to match correctly, as can be seen in the test changes. Differential revision: https://reviews.llvm.org/D66703
  11. [OpenCL] Drop spurious semicolon in generated file; NFC
  12. [SystemZ] Add support for fentry. SystemZAsmPrinter now properly emits function calls to __fentry__. Review: Ulrich Weigand
  13. [ARM] Invert CSEL predicates if the opposite is a simpler constant to materialise This moves ConstantMaterializationCost into ARMBaseInstrInfo so that it can also be used in ISel Lowering, adding codesize values to the computed costs, to be able to compare either approximate instruction counts or codesize costs. It also adds a HasLowerConstantMaterializationCost, which compares the ConstantMaterializationCost of two values, returning true if the first is smaller either in instruction count/codesize, or falling back to the other in the case that they are equal. This is used in constant CSEL lowering to invert the predicate if the opposite is easier to materialise. Differential revision: https://reviews.llvm.org/D66701
  14. Fixit for -Wfinal-dtor-non-final-class
  15. [ARM] Generate 8.1-m CSINC, CSNEG and CSINV instructions. Arm 8.1-M adds a number of related CSEL instructions, including CSINC, CSNEG and CSINV. These choose between two values given the content in CPSR and a condition, performing an increment, negation or inverse of the false value. This adds some selection for them, either from constant values or patterns. It does not include CSEL directly, which is currently not always making code better. It is still useful, but we will have to check more carefully where it should and shouldn't be used. Code by Ranjeet Singh and Simon Tatham, with some modifications from me. Differential revision: https://reviews.llvm.org/D66483
  16. [ARM] Add csel tests. NFC
  17. Added fixit notes for -Wfinal-dtor-non-final-class
  18. [mips] Switch to the `.text` section after emitting asm file preamble Now the last `.section` directive in the MIPS asm file preamble is the `.section .mdebug.abi`. If assembler code injected for example by the LLVM `module asm` or the C ` __asm` directives do not contain explicit switching to the `.text` section it goes to the `.mdebug.abi` section. It might be unexpected to the user and in fact for example breaks building some existing code like FreeBSD libc [1]. The patch forces switching to the `.text` section after emitting MIPS assembler file preamble. [1] https://bugs.llvm.org/show_bug.cgi?id=43119 Fix PR43119. Differential Revision: https://reviews.llvm.org/D67014
  19. [ARM] Fix MVE ldst offset ranges We were using isShiftedInt<7, Shift>(RHSC) to detect the ranges of offsets to fold into MVE loads/stores. The instructions actually take a 7 bit unsigned integer which is either added or subtracted. So something more like isShiftedUInt<7, Shift>(abs(RHSC)). Instead I've changes this to use the isScaledConstantInRange method, same as in SelectT2AddrModeImm7Offset used by pre/post inc, which seemed to already be getting this correct. Differential revision: https://reviews.llvm.org/D66997
  20. [ARM][MVE] Decoding of VMSR doesn't diagnose some unpredictable encodings Decoding of VMSR doesn't diagnose some unpredictable encodings, as the unpredictable bits are not correctly set. Diff-reduce this instruction's internals WRT VMRS so I can see the differences better. Mostly this is s/src/Rt/g. Fill in the "should-be-(0)" bits. Designate the Unpredictable{} bits for both VMRS and VMSR. Patch by Mark Murray! Differential revision: https://reviews.llvm.org/D66938
  21. Bug fix on function epilog optimization (ARM backend) To save a 'add sp,#val' instruction by adding registers to the final pop instruction, the first register transferred by this pop instruction need to be found. If the function to be optimized has a non-void return value, the operand list contains r0 (implicit) which prevents the optimization to take place. Therefore implicit register references should be skipped in the search loop, because this registers are never popped from the stack. Patch by Rainer Herbertz (rOptimizer)! Differential revision: https://reviews.llvm.org/D66730
  22. [ARM] More MVE load/store tests for offsets around the negative limit. NFC
  23. [LV] Fix miscompiles by adding non-header PHI nodes to AllowedExit Summary: Fold-tail currently supports reduction last-vector-value live-out's, but has yet to support last-scalar-value live-outs, including non-header phi's. As it relies on AllowedExit in order to detect them and bail out we need to add the non-header PHI nodes to AllowedExit, otherwise we end up with miscompiles. Solves https://bugs.llvm.org/show_bug.cgi?id=43166 Reviewers: fhahn, Ayal Reviewed By: fhahn, Ayal Subscribers: anna, hiraditya, rkruppe, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67074
  24. [LV] Precommit test case showing miscompile from PR43166. NFC Summary: Precommit test case showing miscompile from PR43166. Reviewers: fhahn, Ayal Reviewed By: fhahn Subscribers: rkruppe, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67072
  25. [ARM NEON] Avoid duplicated decarations Summary: The declaration of arm neon intrinsics that are "big endian safe" print the same code for big and small endian targets. This patch avoids duplicates by checking if an intrinsic is safe to have a single definition. (decreases header 11k lines out of 73k). Reviewers: t.p.northover, ostannard, labrinea Reviewed By: ostannard Subscribers: kristof.beyls, cfe-commits, olista01 Tags: #clang Differential Revision: https://reviews.llvm.org/D66588
  26. [LV] Tail-folding, runtime scev checks Now that we allow tail-folding, not only when we optimise for size, make sure we do not run in this assert. Differential revision: https://reviews.llvm.org/D66932
  27. [RISCV] Correct Logic around ilp32e macros Summary: GCC seperates the `__riscv_float_abi_*` macros and the `__riscv_abi_rve` macro. If the chosen abi is ilp32e, `gcc -march=rv32i -mabi=ilp32i -E -dM` shows that both `__riscv_float_abi_soft` and `__riscv_abi_rve` are set. This patch corrects the compiler logic around these defines. At the moment, this patch will not change clang's behaviour, because we do not accept the `ilp32e` abi yet. Reviewers: luismarques, asb Reviewed By: luismarques Subscribers: rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, pzheng, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D66591
  28. [LV] Tail-folding with runtime memory checks The loop vectorizer was running in an assert when it tried to fold the tail and had to emit runtime memory disambiguation checks. Differential revision: https://reviews.llvm.org/D66803
  29. [MachinePipeliner] Add a way to unit-test the schedule emitter Emitting a schedule is really hard. There are lots of corner cases to take care of; in fact, of the 60+ SWP-specific testcases in the Hexagon backend most of those are testing codegen rather than the schedule creation itself. One issue is that to test an emission corner case we must craft an input such that the generated schedule uses that corner case; sometimes this is very hard and convolutes testcases. Other times it is impossible but we want to test it anyway. This patch adds a simple test pass that will consume a module containing a loop and generate pipelined code from it. We use post-instr-symbols as a way to annotate instructions with the stage and cycle that we want to schedule them at. We also provide a flag that causes the MachinePipeliner to generate these annotations instead of actually emitting code; this allows us to generate an input testcase with: llc < %s -stop-after=pipeliner -pipeliner-annotate-for-testing -o test.mir And run the emission in isolation with: llc < test.mir -run-pass=modulo-schedule-test
  30. [ARM] Select vmla This patch adds vmla selection. Differential revision: https://reviews.llvm.org/D66297
  31. [X86] Simplify the setOperationAction handling for fp_to_uint by improving the Custom handler a bit. This merges the 32-bit and 64-bit mode code to just use Custom for both i32 and i64. We already had most of the handling in the custom handling due to the AVX512 having legal fp_to_uint. Just needed to add the i32->i64 promotion handling. Refactor the fp_to_uint code in the custom handler to simplify the number of times we check things. Tweak cost model tables to match the default handling we were getting due to Expand before.
  32. [X86] Don't use Expand for i32 fp_to_uint on SSE1/2 targets on 32-bit target. Use Custom lowering instead. Fall back to default expansion only when the scalar FP type belongs in an XMM register. This improves lowering for i32 to fp80, and also i32 to double on SSE1 only.
  33. [X86] Add an exhaustive test for i32 fptosi/fptoui across different triples and features.
  34. [LegalizeDAG] Pass DAG to two calls to SDNode::dump in debug prints so that they will print target specific nodes correctly. The dump methods can only print target node names correctly if they can get access to the TLI object.
  35. [X86] Custom promote i32->f80 uint_to_fp on AVX512 64-bit targets. Reuse the same code to promote all i32 uint_to_fp on 64-bit targets to simplify the X86ISelLowering constructor.
  36. [x86] Fix bugs of some intrinsic functions in CLANG : _mm512_stream_ps, _mm512_stream_pd, _mm512_stream_si512 Reviewers: craig.topper, pengfei, LuoYuanke, RKSimon, spatel Reviewed By: RKSimon Subscribers: llvm-commits Patch by Bing Yu (yubing) Differential Revision: https://reviews.llvm.org/D66786
  37. Rename -Wc++20-designator to -Wc++2a-designator for consistency and add some test coverage for the flag.
  38. Split -Wreorder into different warnings for reordering a constructor mem-initializer list and for reordering a designated initializer list.
  39. [CostModel][X86] Add scalar sext/zext cost tests
  40. [X86] Enable fp128 as a legal type with SSE1 rather than with MMX. FP128 values are passed in xmm registers so should be asssociated with an SSE feature rather than MMX which uses a different set of registers. llc enables sse1 and sse2 by default with x86_64. But does not enable mmx. Clang enables all 3 features by default. I've tried to add command lines to test with -sse where possible, but any test that returns a value in an xmm register fails with a fatal error with -sse since we have no defined ABI for that scenario.
Revision 370758 by ibiryukov:
[clangd] Fix a data race in test code

Found by TSan, thanks bkramer for pointing this out.
Change TypePath in RepositoryPath in Workspace
The file was modified/clang-tools-extra/trunk/clangd/unittests/TUSchedulerTests.cpp (diff)clang-tools-extra.src/clangd/unittests/TUSchedulerTests.cpp
Revision 370757 by sammccall:
[clangd] Wrong attribute on debug function in r370746
Change TypePath in RepositoryPath in Workspace
The file was modified/clang-tools-extra/trunk/clangd/FindTarget.cpp (diff)clang-tools-extra.src/clangd/FindTarget.cpp
Revision 370756 by emaste:
compiler-rt: use 64-bit time_t for all FreeBSD archs except i386

At present only i386 has 32-bit time_t on FreeBSD.

Reviewed by: dim
Differential Revision: https://reviews.llvm.org/D66758
Change TypePath in RepositoryPath in Workspace
The file was modified/compiler-rt/trunk/lib/sanitizer_common/sanitizer_platform_limits_freebsd.h (diff)compiler-rt.src/lib/sanitizer_common/sanitizer_platform_limits_freebsd.h
Revision 370755 by emaste:
compiler-rt: use more __sanitizer_time_t on FreeBSD

A few structs were using long for time_t members.  NFC.

Reviewed by: devnexen
Differential Revision: https://reviews.llvm.org/D66756
Change TypePath in RepositoryPath in Workspace
The file was modified/compiler-rt/trunk/lib/sanitizer_common/sanitizer_platform_limits_freebsd.h (diff)compiler-rt.src/lib/sanitizer_common/sanitizer_platform_limits_freebsd.h
Revision 370753 by jonpa:
[SystemZ]  Recognize INLINEASM_BR in backend.

SystemZInstrInfo::analyzeBranch() needs to check for INLINEASM_BR
instructions, or it will crash.

Review: Ulrich Weigand
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp (diff)llvm.src/lib/Target/SystemZ/SystemZInstrInfo.cpp
The file was added/llvm/trunk/test/CodeGen/SystemZ/asm-20.llllvm.src/test/CodeGen/SystemZ/asm-20.ll
Revision 370752 by nico:
gn build: (manually) merge r370499
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/utils/gn/secondary/llvm/test/BUILD.gn (diff)llvm.src/utils/gn/secondary/llvm/test/BUILD.gn
The file was added/llvm/trunk/utils/gn/secondary/llvm/tools/llvm-ifsllvm.src/utils/gn/secondary/llvm/tools/llvm-ifs
The file was added/llvm/trunk/utils/gn/secondary/llvm/tools/llvm-ifs/BUILD.gnllvm.src/utils/gn/secondary/llvm/tools/llvm-ifs/BUILD.gn
Revision 370750 by rksimon:
Fix MSVC "not all control paths return a value" warning. NFCI.
Change TypePath in RepositoryPath in Workspace
The file was modified/clang-tools-extra/trunk/clangd/FindTarget.cpp (diff)clang-tools-extra.src/clangd/FindTarget.cpp
Revision 370749 by nico:
gn build: Merge r370746
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/utils/gn/secondary/clang-tools-extra/clangd/BUILD.gn (diff)llvm.src/utils/gn/secondary/clang-tools-extra/clangd/BUILD.gn
The file was modified/llvm/trunk/utils/gn/secondary/clang-tools-extra/clangd/unittests/BUILD.gn (diff)llvm.src/utils/gn/secondary/clang-tools-extra/clangd/unittests/BUILD.gn
Revision 370746 by sammccall:
[clangd] Add targetDecl(), which determines what declaration an AST node refers to.

Summary:
This is the first part of an effort to "unbundle" our libIndex use into separate
concerns (AST traversal, token<->node mapping, node<->decl mapping,
decl<->decl relationshipes).

Currently, clangd relies on libIndex to associate tokens, AST nodes, and decls.
This leads to rather convoluted implementations of e.g. hover and
extract-function, which are not naturally thought of as indexing applications.

The idea is that by decoupling different concerns, we make them easier
to use, test, and combine, and more efficient when only one part is needed.
There are some synergies between e.g. traversal and finding
relationships between decls, hopefully the benefits outweight these.

Reviewers: kadircet, ilya-biryukov

Subscribers: mgorny, MaskRay, jkorous, arphaman, jfb, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D66751
Change TypePath in RepositoryPath in Workspace
The file was modified/clang-tools-extra/trunk/clangd/CMakeLists.txt (diff)clang-tools-extra.src/clangd/CMakeLists.txt
The file was added/clang-tools-extra/trunk/clangd/FindTarget.cppclang-tools-extra.src/clangd/FindTarget.cpp
The file was added/clang-tools-extra/trunk/clangd/FindTarget.hclang-tools-extra.src/clangd/FindTarget.h
The file was modified/clang-tools-extra/trunk/clangd/unittests/ASTTests.cpp (diff)clang-tools-extra.src/clangd/unittests/ASTTests.cpp
The file was modified/clang-tools-extra/trunk/clangd/unittests/CMakeLists.txt (diff)clang-tools-extra.src/clangd/unittests/CMakeLists.txt
The file was added/clang-tools-extra/trunk/clangd/unittests/FindTargetTests.cppclang-tools-extra.src/clangd/unittests/FindTargetTests.cpp
Revision 370745 by dmgreen:
[ARM] Ignore Implicit CPSR regs when lowering from Machine to MC operands

The code here seems to date back to r134705, when tablegen lowering was first
being added. I don't believe that we need to include CPSR implicit operands on
the MCInst. This now works more like other backends (like AArch64), where all
implicit registers are skipped.

This allows the AliasInst for CSEL's to match correctly, as can be seen in the
test changes.

Differential revision: https://reviews.llvm.org/D66703
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp (diff)llvm.src/lib/Target/ARM/ARMMCInstLower.cpp
The file was modified/llvm/trunk/test/CodeGen/Thumb2/csel.ll (diff)llvm.src/test/CodeGen/Thumb2/csel.ll
The file was modified/llvm/trunk/test/CodeGen/Thumb2/mve-abs.ll (diff)llvm.src/test/CodeGen/Thumb2/mve-abs.ll
The file was modified/llvm/trunk/test/CodeGen/Thumb2/mve-fmath.ll (diff)llvm.src/test/CodeGen/Thumb2/mve-fmath.ll
The file was modified/llvm/trunk/test/CodeGen/Thumb2/mve-minmax.ll (diff)llvm.src/test/CodeGen/Thumb2/mve-minmax.ll
The file was modified/llvm/trunk/test/CodeGen/Thumb2/mve-pred-and.ll (diff)llvm.src/test/CodeGen/Thumb2/mve-pred-and.ll
The file was modified/llvm/trunk/test/CodeGen/Thumb2/mve-pred-bitcast.ll (diff)llvm.src/test/CodeGen/Thumb2/mve-pred-bitcast.ll
The file was modified/llvm/trunk/test/CodeGen/Thumb2/mve-pred-build-var.ll (diff)llvm.src/test/CodeGen/Thumb2/mve-pred-build-var.ll
The file was modified/llvm/trunk/test/CodeGen/Thumb2/mve-pred-ext.ll (diff)llvm.src/test/CodeGen/Thumb2/mve-pred-ext.ll
The file was modified/llvm/trunk/test/CodeGen/Thumb2/mve-pred-loadstore.ll (diff)llvm.src/test/CodeGen/Thumb2/mve-pred-loadstore.ll
The file was modified/llvm/trunk/test/CodeGen/Thumb2/mve-pred-not.ll (diff)llvm.src/test/CodeGen/Thumb2/mve-pred-not.ll
The file was modified/llvm/trunk/test/CodeGen/Thumb2/mve-pred-or.ll (diff)llvm.src/test/CodeGen/Thumb2/mve-pred-or.ll
The file was modified/llvm/trunk/test/CodeGen/Thumb2/mve-pred-xor.ll (diff)llvm.src/test/CodeGen/Thumb2/mve-pred-xor.ll
The file was modified/llvm/trunk/test/CodeGen/Thumb2/mve-vcmp.ll (diff)llvm.src/test/CodeGen/Thumb2/mve-vcmp.ll
The file was modified/llvm/trunk/test/CodeGen/Thumb2/mve-vcmpf.ll (diff)llvm.src/test/CodeGen/Thumb2/mve-vcmpf.ll
The file was modified/llvm/trunk/test/CodeGen/Thumb2/mve-vcmpfr.ll (diff)llvm.src/test/CodeGen/Thumb2/mve-vcmpfr.ll
The file was modified/llvm/trunk/test/CodeGen/Thumb2/mve-vcmpfz.ll (diff)llvm.src/test/CodeGen/Thumb2/mve-vcmpfz.ll
The file was modified/llvm/trunk/test/CodeGen/Thumb2/mve-vcmpr.ll (diff)llvm.src/test/CodeGen/Thumb2/mve-vcmpr.ll
The file was modified/llvm/trunk/test/CodeGen/Thumb2/mve-vcmpz.ll (diff)llvm.src/test/CodeGen/Thumb2/mve-vcmpz.ll
The file was modified/llvm/trunk/test/MC/ARM/thumbv8.1m.s (diff)llvm.src/test/MC/ARM/thumbv8.1m.s
Revision 370744 by svenvh:
[OpenCL] Drop spurious semicolon in generated file; NFC
Change TypePath in RepositoryPath in Workspace
The file was modified/cfe/trunk/utils/TableGen/ClangOpenCLBuiltinEmitter.cpp (diff)clang.src/utils/TableGen/ClangOpenCLBuiltinEmitter.cpp
Revision 370743 by jonpa:
[SystemZ]  Add support for fentry.

SystemZAsmPrinter now properly emits function calls to __fentry__.

Review: Ulrich Weigand
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/SystemZ/SystemZAsmPrinter.cpp (diff)llvm.src/lib/Target/SystemZ/SystemZAsmPrinter.cpp
The file was modified/llvm/trunk/lib/Target/SystemZ/SystemZAsmPrinter.h (diff)llvm.src/lib/Target/SystemZ/SystemZAsmPrinter.h
The file was added/llvm/trunk/test/CodeGen/SystemZ/fentry-insertion.llllvm.src/test/CodeGen/SystemZ/fentry-insertion.ll
Revision 370741 by dmgreen:
[ARM] Invert CSEL predicates if the opposite is a simpler constant to materialise

This moves ConstantMaterializationCost into ARMBaseInstrInfo so that it can
also be used in ISel Lowering, adding codesize values to the computed costs, to
be able to compare either approximate instruction counts or codesize costs.

It also adds a HasLowerConstantMaterializationCost, which compares the
ConstantMaterializationCost of two values, returning true if the first is
smaller either in instruction count/codesize, or falling back to the other in
the case that they are equal.

This is used in constant CSEL lowering to invert the predicate if the opposite
is easier to materialise.

Differential revision: https://reviews.llvm.org/D66701
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (diff)llvm.src/lib/Target/ARM/ARMBaseInstrInfo.cpp
The file was modified/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h (diff)llvm.src/lib/Target/ARM/ARMBaseInstrInfo.h
The file was modified/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (diff)llvm.src/lib/Target/ARM/ARMISelDAGToDAG.cpp
The file was modified/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (diff)llvm.src/lib/Target/ARM/ARMISelLowering.cpp
The file was modified/llvm/trunk/test/CodeGen/Thumb2/csel.ll (diff)llvm.src/test/CodeGen/Thumb2/csel.ll
Revision 370740 by xbolva00:
Fixit for -Wfinal-dtor-non-final-class
Change TypePath in RepositoryPath in Workspace
The file was modified/cfe/trunk/lib/Sema/SemaDeclCXX.cpp (diff)clang.src/lib/Sema/SemaDeclCXX.cpp
The file was modified/cfe/trunk/test/SemaCXX/warn-final-dtor-non-final-class.cpp (diff)clang.src/test/SemaCXX/warn-final-dtor-non-final-class.cpp
Revision 370739 by dmgreen:
[ARM] Generate 8.1-m CSINC, CSNEG and CSINV instructions.

Arm 8.1-M adds a number of related CSEL instructions, including CSINC, CSNEG and CSINV. These choose between two values given the content in CPSR and a condition, performing an increment, negation or inverse of the false value.

This adds some selection for them, either from constant values or patterns. It does not include CSEL directly, which is currently not always making code better. It is still useful, but we will have to check more carefully where it should and shouldn't be used.

Code by Ranjeet Singh and Simon Tatham, with some modifications from me.

Differential revision: https://reviews.llvm.org/D66483
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (diff)llvm.src/lib/Target/ARM/ARMBaseInstrInfo.cpp
The file was modified/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (diff)llvm.src/lib/Target/ARM/ARMISelLowering.cpp
The file was modified/llvm/trunk/lib/Target/ARM/ARMISelLowering.h (diff)llvm.src/lib/Target/ARM/ARMISelLowering.h
The file was modified/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (diff)llvm.src/lib/Target/ARM/ARMInstrFormats.td
The file was modified/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (diff)llvm.src/lib/Target/ARM/ARMInstrInfo.td
The file was modified/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (diff)llvm.src/lib/Target/ARM/ARMInstrThumb2.td
The file was modified/llvm/trunk/test/CodeGen/Thumb2/csel.ll (diff)llvm.src/test/CodeGen/Thumb2/csel.ll
The file was modified/llvm/trunk/test/CodeGen/Thumb2/mve-abs.ll (diff)llvm.src/test/CodeGen/Thumb2/mve-abs.ll
The file was modified/llvm/trunk/test/CodeGen/Thumb2/mve-fmath.ll (diff)llvm.src/test/CodeGen/Thumb2/mve-fmath.ll
The file was modified/llvm/trunk/test/CodeGen/Thumb2/mve-minmax.ll (diff)llvm.src/test/CodeGen/Thumb2/mve-minmax.ll
The file was modified/llvm/trunk/test/CodeGen/Thumb2/mve-pred-and.ll (diff)llvm.src/test/CodeGen/Thumb2/mve-pred-and.ll
The file was modified/llvm/trunk/test/CodeGen/Thumb2/mve-pred-bitcast.ll (diff)llvm.src/test/CodeGen/Thumb2/mve-pred-bitcast.ll
The file was modified/llvm/trunk/test/CodeGen/Thumb2/mve-pred-build-var.ll (diff)llvm.src/test/CodeGen/Thumb2/mve-pred-build-var.ll
The file was modified/llvm/trunk/test/CodeGen/Thumb2/mve-pred-ext.ll (diff)llvm.src/test/CodeGen/Thumb2/mve-pred-ext.ll
The file was modified/llvm/trunk/test/CodeGen/Thumb2/mve-pred-loadstore.ll (diff)llvm.src/test/CodeGen/Thumb2/mve-pred-loadstore.ll
The file was modified/llvm/trunk/test/CodeGen/Thumb2/mve-pred-not.ll (diff)llvm.src/test/CodeGen/Thumb2/mve-pred-not.ll
The file was modified/llvm/trunk/test/CodeGen/Thumb2/mve-pred-or.ll (diff)llvm.src/test/CodeGen/Thumb2/mve-pred-or.ll
The file was modified/llvm/trunk/test/CodeGen/Thumb2/mve-pred-xor.ll (diff)llvm.src/test/CodeGen/Thumb2/mve-pred-xor.ll
The file was modified/llvm/trunk/test/CodeGen/Thumb2/mve-vcmp.ll (diff)llvm.src/test/CodeGen/Thumb2/mve-vcmp.ll
The file was modified/llvm/trunk/test/CodeGen/Thumb2/mve-vcmpf.ll (diff)llvm.src/test/CodeGen/Thumb2/mve-vcmpf.ll
The file was modified/llvm/trunk/test/CodeGen/Thumb2/mve-vcmpfr.ll (diff)llvm.src/test/CodeGen/Thumb2/mve-vcmpfr.ll
The file was modified/llvm/trunk/test/CodeGen/Thumb2/mve-vcmpfz.ll (diff)llvm.src/test/CodeGen/Thumb2/mve-vcmpfz.ll
The file was modified/llvm/trunk/test/CodeGen/Thumb2/mve-vcmpr.ll (diff)llvm.src/test/CodeGen/Thumb2/mve-vcmpr.ll
The file was modified/llvm/trunk/test/CodeGen/Thumb2/mve-vcmpz.ll (diff)llvm.src/test/CodeGen/Thumb2/mve-vcmpz.ll
Revision 370738 by dmgreen:
[ARM] Add csel tests. NFC
Change TypePath in RepositoryPath in Workspace
The file was added/llvm/trunk/test/CodeGen/Thumb2/csel.llllvm.src/test/CodeGen/Thumb2/csel.ll
Revision 370737 by xbolva00:
Added fixit notes for -Wfinal-dtor-non-final-class
Change TypePath in RepositoryPath in Workspace
The file was modified/cfe/trunk/lib/Sema/SemaDeclCXX.cpp (diff)clang.src/lib/Sema/SemaDeclCXX.cpp
The file was modified/cfe/trunk/test/SemaCXX/warn-final-dtor-non-final-class.cpp (diff)clang.src/test/SemaCXX/warn-final-dtor-non-final-class.cpp
Revision 370735 by atanasyan:
[mips] Switch to the `.text` section after emitting asm file preamble

Now the last `.section` directive in the MIPS asm file preamble
is the `.section .mdebug.abi`. If assembler code injected for example
by the LLVM `module asm` or the C ` __asm` directives do not contain
explicit switching to the `.text` section it goes to the `.mdebug.abi`
section. It might be unexpected to the user and in fact for example
breaks building some existing code like FreeBSD libc [1].

The patch forces switching to the `.text` section after emitting MIPS
assembler file preamble.

[1] https://bugs.llvm.org/show_bug.cgi?id=43119

Fix PR43119.

Differential Revision: https://reviews.llvm.org/D67014
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp (diff)llvm.src/lib/Target/Mips/MipsAsmPrinter.cpp
The file was modified/llvm/trunk/test/CodeGen/Mips/start-asm-file.ll (diff)llvm.src/test/CodeGen/Mips/start-asm-file.ll
Revision 370731 by dmgreen:
[ARM] Fix MVE ldst offset ranges

We were using isShiftedInt<7, Shift>(RHSC) to detect the ranges of offsets to
fold into MVE loads/stores. The instructions actually take a 7 bit unsigned
integer which is either added or subtracted. So something more like
isShiftedUInt<7, Shift>(abs(RHSC)).

Instead I've changes this to use the isScaledConstantInRange method, same as in
SelectT2AddrModeImm7Offset used by pre/post inc, which seemed to already be
getting this correct.

Differential revision: https://reviews.llvm.org/D66997
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (diff)llvm.src/lib/Target/ARM/ARMISelDAGToDAG.cpp
The file was modified/llvm/trunk/test/CodeGen/Thumb2/mve-ldst-offset.ll (diff)llvm.src/test/CodeGen/Thumb2/mve-ldst-offset.ll
The file was modified/llvm/trunk/test/CodeGen/Thumb2/mve-loadstore.ll (diff)llvm.src/test/CodeGen/Thumb2/mve-loadstore.ll
Revision 370729 by ostannard:
[ARM][MVE] Decoding of VMSR doesn't diagnose some unpredictable encodings

Decoding of VMSR doesn't diagnose some unpredictable encodings, as the unpredictable bits are not correctly set.

Diff-reduce this instruction's internals WRT VMRS so I can see the differences better. Mostly this is s/src/Rt/g.

Fill in the "should-be-(0)" bits.

Designate the Unpredictable{} bits for both VMRS and VMSR.

Patch by Mark Murray!

Differential revision: https://reviews.llvm.org/D66938
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (diff)llvm.src/lib/Target/ARM/ARMInstrVFP.td
The file was added/llvm/trunk/test/MC/Disassembler/ARM/vmrs-vmsr-invalid.txtllvm.src/test/MC/Disassembler/ARM/vmrs-vmsr-invalid.txt
Revision 370728 by ostannard:
Bug fix on function epilog optimization (ARM backend)

To save a 'add sp,#val' instruction by adding registers to the final pop instruction,
the first register transferred by this pop instruction need to be found.
If the function to be optimized has a non-void return value, the operand list contains
r0 (implicit) which prevents the optimization to take place.
Therefore implicit register references should be skipped in the search loop,
because this registers are never popped from the stack.

Patch by Rainer Herbertz (rOptimizer)!

Differential revision: https://reviews.llvm.org/D66730
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (diff)llvm.src/lib/Target/ARM/ARMBaseInstrInfo.cpp
The file was modified/llvm/trunk/test/CodeGen/ARM/fold-stack-adjust.ll (diff)llvm.src/test/CodeGen/ARM/fold-stack-adjust.ll
Revision 370726 by dmgreen:
[ARM] More MVE load/store tests for offsets around the negative limit. NFC
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/CodeGen/Thumb2/mve-ldst-offset.ll (diff)llvm.src/test/CodeGen/Thumb2/mve-ldst-offset.ll
The file was modified/llvm/trunk/test/CodeGen/Thumb2/mve-ldst-postinc.ll (diff)llvm.src/test/CodeGen/Thumb2/mve-ldst-postinc.ll
The file was modified/llvm/trunk/test/CodeGen/Thumb2/mve-ldst-preinc.ll (diff)llvm.src/test/CodeGen/Thumb2/mve-ldst-preinc.ll
Revision 370721 by bjope:
[LV] Fix miscompiles by adding non-header PHI nodes to AllowedExit

Summary:
Fold-tail currently supports reduction last-vector-value live-out's,
but has yet to support last-scalar-value live-outs, including
non-header phi's. As it relies on AllowedExit in order to detect
them and bail out we need to add the non-header PHI nodes to
AllowedExit, otherwise we end up with miscompiles.

Solves https://bugs.llvm.org/show_bug.cgi?id=43166

Reviewers: fhahn, Ayal

Reviewed By: fhahn, Ayal

Subscribers: anna, hiraditya, rkruppe, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D67074
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h (diff)llvm.src/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h
The file was modified/llvm/trunk/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp (diff)llvm.src/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
The file was modified/llvm/trunk/test/Transforms/LoopVectorize/pr43166-fold-tail-by-masking.ll (diff)llvm.src/test/Transforms/LoopVectorize/pr43166-fold-tail-by-masking.ll
Revision 370720 by bjope:
[LV] Precommit test case showing miscompile from PR43166. NFC

Summary:  Precommit test case showing miscompile from PR43166.

Reviewers: fhahn, Ayal

Reviewed By: fhahn

Subscribers: rkruppe, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D67072
Change TypePath in RepositoryPath in Workspace
The file was added/llvm/trunk/test/Transforms/LoopVectorize/pr43166-fold-tail-by-masking.llllvm.src/test/Transforms/LoopVectorize/pr43166-fold-tail-by-masking.ll
Revision 370716 by dnsampaio:
[ARM NEON] Avoid duplicated decarations

Summary:
The declaration of arm neon intrinsics that are
"big endian safe" print the same code for big
and small endian targets.
This patch avoids duplicates by checking if an
intrinsic is safe to have a single definition.
(decreases header 11k lines out of 73k).

Reviewers: t.p.northover, ostannard, labrinea

Reviewed By: ostannard

Subscribers: kristof.beyls, cfe-commits, olista01

Tags: #clang

Differential Revision: https://reviews.llvm.org/D66588
Change TypePath in RepositoryPath in Workspace
The file was modified/cfe/trunk/utils/TableGen/NeonEmitter.cpp (diff)clang.src/utils/TableGen/NeonEmitter.cpp
Revision 370711 by sjoerdmeijer:
[LV] Tail-folding, runtime scev checks

Now that we allow tail-folding, not only when we optimise for size, make
sure we do not run in this assert.

Differential revision: https://reviews.llvm.org/D66932
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Transforms/Vectorize/LoopVectorize.cpp (diff)llvm.src/lib/Transforms/Vectorize/LoopVectorize.cpp
Revision 370709 by lenary:
[RISCV] Correct Logic around ilp32e macros

Summary:
GCC seperates the `__riscv_float_abi_*` macros and the
`__riscv_abi_rve` macro. If the chosen abi is ilp32e, `gcc -march=rv32i
-mabi=ilp32i -E -dM` shows that both `__riscv_float_abi_soft` and
`__riscv_abi_rve` are set.

This patch corrects the compiler logic around these defines.

At the moment, this patch will not change clang's behaviour, because we do not
accept the `ilp32e` abi yet.

Reviewers: luismarques, asb

Reviewed By: luismarques

Subscribers: rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, pzheng, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D66591
Change TypePath in RepositoryPath in Workspace
The file was modified/cfe/trunk/lib/Basic/Targets/RISCV.cpp (diff)clang.src/lib/Basic/Targets/RISCV.cpp
Revision 370707 by sjoerdmeijer:
[LV] Tail-folding with runtime memory checks

The loop vectorizer was running in an assert when it tried to fold the tail and
had to emit runtime memory disambiguation checks.

Differential revision: https://reviews.llvm.org/D66803
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Transforms/Vectorize/LoopVectorize.cpp (diff)llvm.src/lib/Transforms/Vectorize/LoopVectorize.cpp
Revision 370705 by jamesm:
[MachinePipeliner] Add a way to unit-test the schedule emitter

Emitting a schedule is really hard. There are lots of corner cases to take care of; in fact, of the 60+ SWP-specific testcases in the Hexagon backend most of those are testing codegen rather than the schedule creation itself.

One issue is that to test an emission corner case we must craft an input such that the generated schedule uses that corner case; sometimes this is very hard and convolutes testcases. Other times it is impossible but we want to test it anyway.

This patch adds a simple test pass that will consume a module containing a loop and generate pipelined code from it. We use post-instr-symbols as a way to annotate instructions with the stage and cycle that we want to schedule them at.

We also provide a flag that causes the MachinePipeliner to generate these annotations instead of actually emitting code; this allows us to generate an input testcase with:

  llc < %s -stop-after=pipeliner -pipeliner-annotate-for-testing -o test.mir

And run the emission in isolation with:

  llc < test.mir -run-pass=modulo-schedule-test
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/CodeGen/ModuloSchedule.h (diff)llvm.src/include/llvm/CodeGen/ModuloSchedule.h
The file was modified/llvm/trunk/include/llvm/InitializePasses.h (diff)llvm.src/include/llvm/InitializePasses.h
The file was modified/llvm/trunk/lib/CodeGen/CodeGen.cpp (diff)llvm.src/lib/CodeGen/CodeGen.cpp
The file was modified/llvm/trunk/lib/CodeGen/MachinePipeliner.cpp (diff)llvm.src/lib/CodeGen/MachinePipeliner.cpp
The file was modified/llvm/trunk/lib/CodeGen/ModuloSchedule.cpp (diff)llvm.src/lib/CodeGen/ModuloSchedule.cpp
The file was added/llvm/trunk/test/CodeGen/Hexagon/pipelinerllvm.src/test/CodeGen/Hexagon/pipeliner
The file was added/llvm/trunk/test/CodeGen/Hexagon/pipeliner/swp-phi-start.mirllvm.src/test/CodeGen/Hexagon/pipeliner/swp-phi-start.mir
Revision 370704 by samtebbs:
[ARM] Select vmla

This patch adds vmla selection.

Differential revision: https://reviews.llvm.org/D66297
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/ARM/ARMInstrMVE.td (diff)llvm.src/lib/Target/ARM/ARMInstrMVE.td
The file was added/llvm/trunk/test/CodeGen/Thumb2/mve-vmla.llllvm.src/test/CodeGen/Thumb2/mve-vmla.ll
Revision 370700 by ctopper:
[X86] Simplify the setOperationAction handling for fp_to_uint by improving the Custom handler a bit.

This merges the 32-bit and 64-bit mode code to just use Custom
for both i32 and i64. We already had most of the handling in
the custom handling due to the AVX512 having legal fp_to_uint.
Just needed to add the i32->i64 promotion handling. Refactor
the fp_to_uint code in the custom handler to simplify the
number of times we check things.

Tweak cost model tables to match the default handling we were
getting due to Expand before.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (diff)llvm.src/lib/Target/X86/X86ISelLowering.cpp
The file was modified/llvm/trunk/lib/Target/X86/X86TargetTransformInfo.cpp (diff)llvm.src/lib/Target/X86/X86TargetTransformInfo.cpp
Revision 370699 by ctopper:
[X86] Don't use Expand for i32 fp_to_uint on SSE1/2 targets on 32-bit target.

Use Custom lowering instead. Fall back to default expansion only
when the scalar FP type belongs in an XMM register. This improves
lowering for i32 to fp80, and also i32 to double on SSE1 only.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (diff)llvm.src/lib/Target/X86/X86ISelLowering.cpp
The file was modified/llvm/trunk/test/CodeGen/X86/scalar-fp-to-i32.ll (diff)llvm.src/test/CodeGen/X86/scalar-fp-to-i32.ll
Revision 370698 by ctopper:
[X86] Add an exhaustive test for i32 fptosi/fptoui across different triples and features.
Change TypePath in RepositoryPath in Workspace
The file was added/llvm/trunk/test/CodeGen/X86/scalar-fp-to-i32.llllvm.src/test/CodeGen/X86/scalar-fp-to-i32.ll
Revision 370694 by ctopper:
[LegalizeDAG] Pass DAG to two calls to SDNode::dump in debug prints so that they will print target specific nodes correctly.

The dump methods can only print target node names correctly if
they can get access to the TLI object.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (diff)llvm.src/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Revision 370693 by ctopper:
[X86] Custom promote i32->f80 uint_to_fp on AVX512 64-bit targets.

Reuse the same code to promote all i32 uint_to_fp on 64-bit targets
to simplify the X86ISelLowering constructor.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (diff)llvm.src/lib/Target/X86/X86ISelLowering.cpp
The file was modified/llvm/trunk/test/CodeGen/X86/scalar-int-to-fp.ll (diff)llvm.src/test/CodeGen/X86/scalar-int-to-fp.ll
Revision 370691 by pengfei:
[x86] Fix bugs of some intrinsic functions in CLANG : _mm512_stream_ps, _mm512_stream_pd, _mm512_stream_si512

Reviewers: craig.topper, pengfei, LuoYuanke, RKSimon, spatel

Reviewed By: RKSimon

Subscribers: llvm-commits

Patch by Bing Yu (yubing)

Differential Revision: https://reviews.llvm.org/D66786
Change TypePath in RepositoryPath in Workspace
The file was modified/cfe/trunk/lib/Headers/avx512fintrin.h (diff)clang.src/lib/Headers/avx512fintrin.h
The file was modified/cfe/trunk/test/CodeGen/avx512f-builtins.c (diff)clang.src/test/CodeGen/avx512f-builtins.c
Revision 370689 by rsmith:
Rename -Wc++20-designator to -Wc++2a-designator for consistency and add
some test coverage for the flag.
Change TypePath in RepositoryPath in Workspace
The file was modified/cfe/trunk/include/clang/Basic/DiagnosticGroups.td (diff)clang.src/include/clang/Basic/DiagnosticGroups.td
The file was modified/cfe/trunk/test/SemaCXX/cxx2a-initializer-aggregates.cpp (diff)clang.src/test/SemaCXX/cxx2a-initializer-aggregates.cpp
Revision 370688 by rsmith:
Split -Wreorder into different warnings for reordering a constructor
mem-initializer list and for reordering a designated initializer list.
Change TypePath in RepositoryPath in Workspace
The file was modified/cfe/trunk/include/clang/Basic/DiagnosticGroups.td (diff)clang.src/include/clang/Basic/DiagnosticGroups.td
The file was modified/cfe/trunk/include/clang/Basic/DiagnosticSemaKinds.td (diff)clang.src/include/clang/Basic/DiagnosticSemaKinds.td
The file was modified/cfe/trunk/test/SemaCXX/cxx2a-initializer-aggregates.cpp (diff)clang.src/test/SemaCXX/cxx2a-initializer-aggregates.cpp
Revision 370684 by rksimon:
[CostModel][X86] Add scalar sext/zext cost tests
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/Analysis/CostModel/X86/extend.ll (diff)llvm.src/test/Analysis/CostModel/X86/extend.ll
Revision 370682 by ctopper:
[X86] Enable fp128 as a legal type with SSE1 rather than with MMX.

FP128 values are passed in xmm registers so should be asssociated
with an SSE feature rather than MMX which uses a different set
of registers.

llc enables sse1 and sse2 by default with x86_64. But does not
enable mmx. Clang enables all 3 features by default.

I've tried to add command lines to test with -sse
where possible, but any test that returns a value in an xmm
register fails with a fatal error with -sse since we have no
defined ABI for that scenario.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (diff)llvm.src/lib/Target/X86/X86ISelLowering.cpp
The file was added/llvm/trunk/test/CodeGen/X86/atomic-non-integer-fp128.llllvm.src/test/CodeGen/X86/atomic-non-integer-fp128.ll
The file was modified/llvm/trunk/test/CodeGen/X86/atomic-non-integer.ll (diff)llvm.src/test/CodeGen/X86/atomic-non-integer.ll
The file was modified/llvm/trunk/test/CodeGen/X86/atomicf128.ll (diff)llvm.src/test/CodeGen/X86/atomicf128.ll
The file was modified/llvm/trunk/test/CodeGen/X86/extract-store.ll (diff)llvm.src/test/CodeGen/X86/extract-store.ll
The file was modified/llvm/trunk/test/CodeGen/X86/fp128-cast.ll (diff)llvm.src/test/CodeGen/X86/fp128-cast.ll
The file was modified/llvm/trunk/test/CodeGen/X86/fp128-select.ll (diff)llvm.src/test/CodeGen/X86/fp128-select.ll
The file was modified/llvm/trunk/test/CodeGen/X86/vec_fp_to_int.ll (diff)llvm.src/test/CodeGen/X86/vec_fp_to_int.ll